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Details, datasheet, quote on part number:650-07C
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Datasheet text preview:
PRELIMINARY INFORMATION
ICS650-07C N e t w o r k i n g Clock Source
Description
The ICS650-07C is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25.00 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking chips, PCI devices, SDRAM, and ASICs. The ICS650-07C outputs all have 0 ppm synthesis error. See the MK74CB214, ICS551, and ICS552-01 for non-PLL buffer devices which produce multiple low-skew copies of these output clocks. See the ICS570, ICS9112-16/17/18 for zero delay buffers that can synchronize outputs and other needed clocks.
Features
· Packaged in 20 pin narrow (150 mil) SSOP (QSOP) · 12.5 MHz or 25.00 MHz fundamental crystal or clock input · Six output clocks with selectable frequencies · SDRAM frequencies of 67, 83, 100, and 133 MHz · Buffered crystal reference output · Zero ppm synthesis error in all clocks · Ideal for PMC-Sierra's ATM switch chips · Full CMOS output swing with 25 mA output drive capability at TTL levels · Advanced, low power, sub-micron CMOS process · 3.0V to 5.5V operating voltage
Block Diagram
VDD
GND
2 2
2
Output Buffer
CLKA1 CLKA2 CLKB1 CLKB2 CLKC1 CLKC2 REFOUT
ACS1,0 BCS1,0 CCS 12.5 MHz or 25.00 MHz crystal or clock
X1
÷2 2 Clock Synthesis and Control Circuitry ÷2
Output Buffer Output Buffer Output Buffer Output Buffer Output Buffer Output Buffer
X2
Clock Buffer/ Crystal Oscillator
OE (all outputs)
Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board).
1 Revision 101399 Printed 11/28/00 Integrated Circuit Systems, Inc. · 525 Race Street · San Jose · CA · 95126·(408)295-9800tel · www.icst.com
MDS 650-07C A
PRELIMINARY INFORMATION
ICS650-07C N e t w o r k i n g Clock Source
For a 25 MHz fundamental crystal or clock input, the following four tables apply : A Clocks Select Table (outputs in MHz)
ACS1 0 0 0 1 1 1 ACS0 0 M 1 0 M 1 CLKA1 100 Test 75 33.3333 Test 66.6667 CLKA2 off (low) Test off (low) 16.6667 Test 33.3333
B Clocks Select Table (outputs in MHz)
BCS1 0 0 0 1 1 1 BCS0 0 M 1 0 M 1 CLKB1 Test 66.6667 100 83.3333 Test 133.3333 CLKB2 Test 33.3333 50 41.6667 Test 66.6667
C Clocks Select Table (outputs in MHz)
CCS 0 M 1 CLKC1 125 Test 75 CLKC2 125 Test 75 REFOUT 25 MHz
0 = connect directly to GND M = leave unconnected (automatically self biases to VDD/2) 1 = connect directly to VDD
For a 12.5 MHz crystal or clock input, the following four tables apply : A Clocks Select Table (outputs in MHz)
ACS1 0 0 0 1 1 1 ACS0 0 M 1 0 M 1 CLKA1 50 Test 37.5 16.6667 Test 33.3333 CLKA2 off (low) Test off (low) 8.3333 Test 16.6667
B Clocks Select Table (outputs in MHz)
BCS1 0 0 0 1 1 1 BCS0 0 M 1 0 M 1 CLKB1 Test 33.3333 50 41.6667 Test 66.6667 CLKB2 Test 16.6667 25 20.8333 Test 33.3333
C Clocks Select Table (outputs in MHz)
CCS 0 M 1 CLKC1 62.5 Test 37.5 CLKC2 62.5 Test 37.5 REFOUT 12.5 MHz
0 = connect directly to GND M = leave unconnected (automatically self biases to VDD/2) 1 = connect directly to VDD
2 Revision 101399 Printed 11/28/00 Integrated Circuit Systems, Inc. · 525 Race Street · San Jose · CA · 95126·(408)295-9800tel · www.icst.com
MDS 650-07C A
PRELIMINARY INFORMATION
ICS650-07C N e t w o r k i n g Clock Source
Pin Assignment
ACS0 X2 X1/ICLK VDD ACS1 GND CLKC1 CLKC2 CLKB2 CLKB1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 BCS1 BCS0 REFOUT CLKA1 VDD OE GND CLKA2 DC CCS
20 pin (150 mil) SSOP Pin Descriptions
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name ACS0 X2 X1/ICLK VDD ACS1 GND CLKC1 CLKC2 CLKB2 CLKB1 CCS DC CLKA2 GND OE VDD CLKA1 REFOUT BCS0 BCS1 Type TI XO XI P I P O O O O TI O P I P O O TI I Description A Clock Select 0. Selects outputs on CLKA1 and CLKA2 per table on page 2. Crystal connection. Connect to a crystal or leave unconnected for a clock input. Crystal connection. Connect to a fundamental crystal or clock input. Connect to +3.3 V or +5 V. Must be same as other VDD. A Clock Select 1. Selects outputs on CLKA1 and CLKA2 per table on page 2. Connect to ground. Clock C output 1. Depends on setting of CCS per table on page 2. Clock C output 2. Depends on setting of CCS per table on page 2. Same as CLKC1. Clock B output 2. Depends on setting of BCS1, 0 per table on page 2. Clock B output 1. Depends on setting of BCS1, 0 per table on page 2. Clock C Select pin. Selects outputs on CLKC1 and CLKC2 per table on page 2. Don't Connect. Do not connect anything to this pin. Clock A output 2. Depends on setting of ACS1, 0 per table on page 2. Connect to ground. Output Enable. Tri-states all outputs when low. Connect to +3.3 V or +5 V. Must be same as other VDD. Clock A output 1. Depends on setting of ACS1, 0 per table on page 2. Buffered Reference clock Output. Same frequency as crystal or clock input. B Clock Select 0. Selects outputs on CLKB1 and CLKB2 per table on page 2. B Clock Select 1. Selects outputs on CLKB1 and CLKB2 per table on page 2.
Key: TI = tri-level input; XI, XO = crystal connections; I = Input with internal pull-up resistor; O = Output; P = power supply connection 3 Revision 101399 Printed 11/28/00 Integrated Circuit Systems, Inc. · 525 Race Street · San Jose · CA · 95126·(408)295-9800tel · www.icst.com
MDS 650-07C A
PRELIMINARY INFORMATION
ICS650-07C N e t w o r k i n g Clock Source
Typical Maximum 7 VDD+0.5 70 85 260 150 5.5 VDD/2 VDD/2 VDD/2 - 1 0.5 2 0.8 Units V V °C °C °C °C V V V V V V V V V V mA mA k MHz ns ns % ppm ps
Electrical Specifications
Parameter Supply voltage, VDD Inputs and Clock Outputs Ambient Operating Temperature Ambient Operating Temperature, I version Soldering Temperature Storage temperature Operating Voltage, VDD Input High Voltage, VIH, X1 pin only Input Low Voltage, VIL, X1 pin only Input High Voltage, VIH, all TI type inputs Input Low Voltage, VIL, all TI type inputs Input High Voltage, VIH, all I type inputs Input Low Voltage, VIL, all I type inputs Output High Voltage, VOH Output Low Voltage, VOL Output High Voltage, VOH, CMOS level Operating Supply Current, IDD Short Circuit Current Internal pull-up resistor Input Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Frequency error Absolute Jitter, short term Notes: Conditions Referenced to GND Referenced to GND Industrial temp Max of 20 seconds Minimum
ABSOLUTE ABSOLUTE MAXIMUM RATINGS (note 1)
-0.5 0 -40 -65 3 VDD/2 + 1 VDD-0.5
DC CHARACTERISTICS (VDD = 5.0V unless noted)
Clock input Clock input
IOH=-25mA IOL=25mA IOH=-8mA No Load Each output ACS1, BCS1, OE
2.4 0.4 VDD-0.4 60 ±100 200 10 12.5 or 25 27 1.5 1.5 60 0
AC CHARACTERISTICS (VDD = 5.0V unless noted)
0.8 to 2.0V 2.0 to 0.8V At VDD/2 All clocks Variation from mean
40
50 150
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
External Components
The ICS650-07C requires a minimum number of external components for proper operation. Decoupling capacitors of 0.01µF should be connected between each VDD and GND (pins 4 and 6, pins 16 and 14), as close to the ICS650-07 as possible. A series termination resistor of 33 may be used for each clock output. The crystal must be connected as close to the chip as possible. The crystal should be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the following equation, where CL is the crystal load capacitance: Crystal caps (pF) = (CL -6) x 2. So for a crystal with 16 pF load capacitance, two 20 pF caps should be used. 4 Revision 101399 Printed 11/28/00 Integrated Circuit Systems, Inc. · 525 Race Street · San Jose · CA · 95126·(408)295-9800tel · www.icst.com
MDS 650-07C A
PRELIMINARY INFORMATION
ICS650-07C N e t w o r k i n g Clock Source
Package Outline and Package Dimensions (For current dimensional specifications, see JEDEC Publication No. 95.)
20 pin SSOP
Symbol A A1 b c D e E E1 L Inches Min Max 0.053 0.069 0.004 0.010 0.008 0.012 0.007 0.010 0.337 0.344 .025 BSC 0.228 0.244 0.150 0.157 0.016 0.050 Millimeters Min Max 1.35 1.75 0.10 0.25 0.20 0.30 0.19 0.25 8.56 8.74 0.635 BSC 5.79 6.20 3.81 3.99 0.41 1.27
E1
E
INDEX AREA
1
2
D A1 e b c A L
Ordering Information
Part/Order Number ICS650R-07 ICS650R-07T ICS650R-07I ICS650R-07IT Marking ICS650R-07 ICS650R-07 ICS650R-07I ICS650R-07I Shipping packaging tubes tape and reel tubes tape and reel Package 20 pin SSOP 20 pin SSOP 20 pin SSOP 20 pin SSOP Temperature 0-70°C 0-70°C -40 to +85°C -40 to +85°C
Note: The C on the data sheet (ICS650-07C) is not significant when ordering this chip.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
5 Revision 101399 Printed 11/28/00 Integrated Circuit Systems, Inc. · 525 Race Street · San Jose · CA · 95126·(408)295-9800tel · www.icst.com
MDS 650-07C A
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