|
Details, datasheet, quote on part number:8516EY
| |
Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
FEATURES
· 16 Differential LVDS outputs · CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL · Maximum output frequency: 700MHz · Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias networks · Translates any single-ended input signal to LVDS with resistor bias on nCLK input · Multiple output enable inputs for disabling unused outputs in reduced fanout applications · LVDS compatible · Output skew: 90ps (maximum) · Part-to-part skew: 500ps (maximum) · Propagation delay: 2.4ns (maximum) · 3.3V operating supply · 0°C to 70°C ambient operating temperature · Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8516 is a low skew, high performance 1-to-16 Differential-to-LVDS Clock Distribution H iPer Cl ockSTM C h i p and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8516 CLK, nCLK pair can accept any differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the ICS8516 provides a low power, low noise, pointto-point solution for distributing clock signals over controlled impedances of 100.
,&6
Dual output enable inputs allow the ICS8516 to be used in a 1-to-16 or 1-to-8 input/output mode. Guaranteed output and part-to-part skew specifications make the ICS8516 ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK nCLK
PIN ASSIGNMENT
Q9 nQ9 Q8 nQ8 GND OE2 OE1 GND nQ7 Q7 nQ6 Q6
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7
Q15 nQ15 Q14 nQ14 Q13 nQ13 Q12 nQ12 Q11 nQ11 Q10 nQ10 Q9 nQ9 Q8 nQ8
VD D nQ5 Q5 nQ4 Q4 VD D GND nQ3 Q3 nQ2 Q2 VD D
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
ICS8516
VDD nQ10 Q10 nQ11 Q11 VDD GND nQ12 Q12 nQ13 Q13 VDD
OE1 OE2
48-Lead LQFP 7mm x 7mm x 1.4mm body package Y Package Top View
8516FY
www.icst.com/products/hiperclocks.html
1
nQ14 Q14 nQ15 Q15 GND CLK nCLK GND Q0 nQ0 Q1 nQ1
REV. A MARCH 31, 2003
Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Type Power Output Output Power Output Output Output Output Input Input Output Output Output Output Output Output Output Output Pullup Pulldown Description Positive supply pins. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Power supply ground. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Inver ting differential clock input. Non-inver ting differential clock input. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 6, 12, 25, 31, 36 2, 3 4, 5 7, 17, 20, 30, 41, 44 8, 9 10, 11 13, 14 15, 16 18 19 21, 22 23, 24 26, 27 28, 29 32, 33 34, 35 37, 38 39, 40 Name VDD nQ5, Q5 nQ4, Q4 GND nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 nCLK CLK Q15, nQ15 Q14, nQ14 Q13, nQ13 Q12, nQ12 Q11, nQ11 Q10, nQ10 Q9, nQ9 Q8, nQ8
Differential output pair. LVDS interface levels. Output enable. OE2 controls outputs Q8, nQ8 thru Q15, nQ15; 42, 43 OE2, OE1 Input Pullup OE1 controls outputs Q0, nQ0 thru Q7, nQ7. LVCMOS/LVTTL interface levels. 45, 46 Q7, nQ7 Output Differential output pair. LVDS interface levels. 47, 48 Q6, nQ6 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8516FY
www.icst.com/products/hiperclocks.html
2
REV. A MARCH 31, 2003
Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Test Conditions Minimum Typical 51 51 4 Maximum 4 Units pF K K pF
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output)
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs OE1 0 1 0 1 OE2 0 0 1 1 Q0:Q7 Hi Z ACTIVE Hi Z ACTIVE nQ0:nQ7 Hi Z ACTIVE Hi Z ACTIVE Outputs Q8:Q15 Hi Z Hi Z ACTIVE ACTIVE nQ8:nQ15 Hi Z Hi Z ACTIVE ACTIVE
In the active mode, the state of the outputs are a function of the CLK and nCLK inputs as described in Table 3B.
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q15 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0:nQ15 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
8516FY
www.icst.com/products/hiperclocks.html
3
REV. A MARCH 31, 2003
Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 47.9°C/W (0 lfpm) -65°C to 150°C N O T E : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
Symbol VDD IDD Parameter Positive Supply Voltage Static Power Supply Current RL = 100 No Load Test Conditions Minimum 3.135 Typical 3.3 135 60 Maximum 3.465 165 75 Units V mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current OE1, OE2 OE1, OE2 OE1, OE2 OE1, OE2 VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -150 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 5 Units V V µA µA
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VIN = VDD = 3.465V VIN = VDD = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units µA µA µA µA V V
Peak-to-Peak Voltage 0.15 Common Mode Input Voltage; VCMR GND + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined ast VIH.
8516FY
www.icst.com/products/hiperclocks.html
4
REV. A MARCH 31, 2003
Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Test Conditions Minimum 250 1.125 -10 -1 Typical 400 1.4 Maximum 600 50 1.6 50 +10 +1 -5.5 -12 Units mV mV V mV µA µA mA mA
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
Symbol VOD VOD VOS VOS IOZ IOFF IOSD IOS/IOSB Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change High Impedance Leakage Current Power Off Leakage Differential Output Shor t Circuit Current Output Shor t Circuit Current
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 5 Output Disable Time; NOTE 5 20% to 80% 100 45 50 1.6 2.0 Test Conditions Minimum Typical Maximum 700 2.4 90 500 550 55 5 5 Units MHz ns ps ps ps % ns ns
tsk(o) tsk(pp)
tR/tF odc tPZL, tPZH tPLZ, tPHZ
NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
8516FY
www.icst.com/products/hiperclocks.html
5
REV. A MARCH 31, 2003
|
|
