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Details, datasheet, quote on part number:8602AY
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Datasheet text preview:
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8602
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
FEATURES
· Fully integrated PLL · 9 LVCMOS outputs, 7 typical output impedance · CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL · Output frequency range: 12.5MHz to 250MHz · Input frequency range: 12.5MHz to 250MHz · VCO range: 200MHz to 500MHz · External feedback for "zero delay" clock regeneration with configurable frequencies · Cycle-to-cycle jitter: 36ps (typical) · Output skew: 125ps (maximum) · Static Phase Offset: TBD±100ps (typical) · 3.3V supply voltage · 0°C to 70°C ambient operating temperature
GENERAL DESCRIPTION
The ICS8602 is a high performance, low skew, ,&6 1-to-9 Differential-to-LVCMOS zero delay buffer H iPer Cl ockSTM and a member of the HiPerClockSTM family of High Performance Clocks Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels. The VCO operates at a frequency range of 200MHz to 500MHz. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be doubled by utilizing the ability of the outputs to drive two series terminated lines. The differential reference clock input will accept any differential signal levels.
BLOCK DIAGRAM
PIN ASSIGNMENT
PLL_SEL VD D O VD D O GND GND Q6 Q8 Q7
Q0 SEL0 SEL1 Q1 VDDA Q2 ÷2 ÷4 ÷8 ÷16 Q3 Q4 Q5 Q6 FB_IN PLL_SEL MR / nOE Q7 Q8 VD D CLK nCLK GND DIV_SEL0 DIV_SEL1 GND 1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23 22 VD D O Q5 GND Q4 VD D O Q3 GND MR / nOE
0 CLK nCLK PLL 1
ICS8602
21 20 19 18 17
9 10 11 12 13 14 15 16
FB_IN VD D O Q0 GND Q1 VD D O Q2 GND
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8602BY
www.icst.com/products/hiperclocks.html
1
REV. E OCTOBER 9, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8602
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
Type Power Power Input Input Power Input Input Power Output Pulldown Pullup Description Analog supply pin. Core supply pin. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Power supply ground. Determines output divider valued in Table 3. LVCMOS / LVTTL interface levels. Feedback input to phase detector for regenerating clocks Pulldown with "zero delay". LVCMOS / LVTTL interface levels. Output supply pins. Clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. Master reset and output enable. When LOW, output drivers are enabled. When HIGH, output drivers are Pulldown in HiZ and dividers are reset. LVCMOS / LVTTL interface levels. Selects between the PLL and the reference clock as the input to the dividers. When HIGH, selects PLL. Pullup When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5, 8, 12 16, 18, 22, 25, 29 6, 7 9 10, 14, 20, 24, 27, 31 11, 13, 15, 19, 21, 23, 26, 28, 30 17 Name VDDA VDD CLK nCLK GND DIV_SEL0, DIV_SEL1 FB_IN VDDO Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8 MR/nOE
Input
32
PLL_SEL
Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance 51 51 VDDA, VDD, VDDO = 3.47V TBD 7 Test Conditions Minimum Typical Maximum 4 Units pF K K pF
TABLE 3A. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 1
DIV_SEL1 0 0 1 1 DIV_SEL0 0 1 0 1 Input/Output Frequency Range (MHz) Minimum Maximum 100 50 25 12.5 250 125 62.5 31.25
TABLE 3B. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 0
DIV_SEL1 0 0 1 1 DIV_SEL0 0 1 0 1 Input/Output Frequency Range (MHz) fIN fOUT fIN fIN fIN fIN fIN/2 fIN/4 fIN/8 fIN/16
8602BY
www.icst.com/products/hiperclocks.html
2
REV. E OCTOBER 9, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8602
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx 4.6V Inputs, VI -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V Outputs VO Ambient Operating Temperature 42.1°C (0 lfpm) Storage Temperature -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 40 10 160 Maximum 3.465 3.465 3.465 Units V V V mA mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter VIH VIL IIH Input High Voltage Input Low Voltage Input High Current DIV_SEL0, DIV_SEL1, FB_IN, MR/nOE PLL_SEL DIV_SEL0, DIV_SEL1, FB_IN, MR/nOE PLL_SEL VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 2.6 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 5 Units V V µA µA µA µA V
IIL VOH
Input Low Current
Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, 3.3V Output Load Test Circuit.
8602BY
www.icst.com/products/hiperclocks.html
3
REV. E OCTOBER 9, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8602
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
Test Conditions CLK nCLK CLK nCLK VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465, VIN = 0V VDD = 3.465, VIN = 0V -5 -150 0.15 GND + 0.5 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units µA µA µA µA V V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter IIH IIL VPP VCMR Input High Current Input Low Current
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2
NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum voltage for CLK, nCLK is VDD + 0.3V.
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol fMAX tpLH Parameter Output Frequency Propagation Delay, Low-to-High; NOTE 1 Static Phase Offset; NOTE 2 Output Skew; NOTE 3, 4 Cycle-to-Cycle Jitter ; NOTE 4 PLL Lock Time Output Rise Time Output Fall Time 20% to 80% @ 50MHz 20% to 80% @ 50MHz 400 400 Test Conditions PLL_SEL=0V, 0MHz f 250MHz PLL_SEL = 3.3V, fREF = 133MHz, fVCO = 266MHz PLL_SEL = 3.3V, fREF = 50MHz, fVCO = 100MHz Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 Minimum Typical Maximum 250 TBD TBD±100 TBD±100 125 36 1 950 950 TBD Units MHz ns ps ps ps ps ms ps ps %
t(Ø)
tsk(o) tjit(cc)
tL tR tF
odc Output Duty Cycle f = 250MHz 50 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8602BY
www.icst.com/products/hiperclocks.html
4
REV. E OCTOBER 9, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8602
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
VDD, VDDA, V DDO
SCOPE
LVCMOS
Qx
GND
-1.65V±5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
VDD
nCLK V CLK
PP
Cross Points
V
CMR
GND
DIFFERENTIAL INPUT LEVEL
8602BY
www.icst.com/products/hiperclocks.html
5
REV. E OCTOBER 9, 2002
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