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Part: 8634AY-01
Category:
Timing Circuits
-> Clock Buffers
Description:
Company: Integrated Circuit System
Datasheet: Download 8634AY-01 datasheet File size : 104 kB
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Integrated Circuit Systems, Inc.
ICS8634-01
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER
FEATURES
· 5 differential 3.3V LVPECL outputs · Selectable differential clock inputs · CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL · Output frequency range: 31.25MHz to 700MHz · Input frequency range: 31.25MHz to 700MHz · VCO range: 250MHz to 700MHz · External feedback for "zero delay" clock regeneration · Cycle-to-cycle jitter: 25ps (maximum) · Output skew: 25ps (maximum) · PLL reference zero delay: 50ps ± 100ps · 3.3V operating supply · 0°C to 70°C ambient operating temperature · Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8634-01 is a high performance 1-to-5 Differential-to-3.3V LVPECL Zero Delay Buffer and a H iPerC lockSTM member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8634-01 has two selectable clock inputs. The CLKx, nCLKx pair can accept most standard differential input levels. Utilizing one of the outputs as feedback to the PLL, output frequencies up to 700MHz can be regenerated with zero delay with respect to the input. Dual reference clock inputs support redundant clock or multiple reference applications.
,&6
BLOCK DIAGRAM
Q0 nQ0 PLL_SEL ÷4, ÷8 0 1 1 Q3 nQ3 Q1 nQ1 0 Q2 nQ2
PIN ASSIGNMENT
PLL_SEL VCCO VCCA nQ4 VCC VEE VEE
CLK0 nCLK0 CLK1 nCLK1 CLK_SEL FB_IN nFB_IN
32 31 30 29 28 27 26 25 SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL MR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VCC nFB_IN FB_IN VEE VEE nQ0 Q0 V CCO
Q4
24 23 22
V CCO Q3 nQ3 Q2 nQ2 Q1 nQ1 V CCO
PLL
Q4 nQ4
ICS8634-01
21 20 19 18 17
SEL0 SEL1 MR
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
8634BY-01
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1
REV. B MARCH 5, 2003
Integrated Circuit Systems, Inc.
ICS8634-01
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER
Type Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 Name SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL Input Input Input Input Input Input Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When LOW, selects CLK0, nCLK0. Pulldown When HIGH, selects CLK1, nCLK1. LVCMOS / LVTTL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx to go Pulldown high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Core supply pins. Pullup Feedback input to phase detector for regenerating clocks with "zero delay". Pulldown Feedback input to phase detector for regenerating clocks with "zero delay". Negative supply pins. Differential output pair. LVPECL interface levels. Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.. Differential output pair. LVPECL interface levels. Analog supply pin. Selects between the PLL and the reference clock as the input to the dividers. When HIGH, selects PLL. When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
8 9, 32 10 11 12, 13 28, 29 14, 15 16. 17, 24, 25 18, 19 20, 21 22, 23 26, 27 30 31
MR VCC nFB_IN FB_IN VEE nQ0, Q0 VCCO nQ1, Q1 nQ2, Q2 nQ3, Q3 nQ4, Q4 VCCA PLL_SEL
Input Power Input Input Power Output Power Output Output Output Output Power Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs SEL1 SEL0 0 0 1 0 1 0 Reference Frequency Range (MHz)* 250 - 700 125 - 350 62.5 - 175 Outputs PLL_SEL = 1 PLL Enable Mode Q0:Q4, nQ0:nQ4 ÷1 ÷1 ÷1 ÷1
TABLE 3B. PLL BYPASS FUNCTION TABLE
Inputs SEL1 SEL0 0 0 1 1 0 1 0 1 Outputs PLL_SEL = 0 PLL Bypass Mode Q0:Q4, nQ0:nQ4 ÷4 ÷4 ÷4 ÷8
1 1 31.25 - 87.5 *NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
8634BY-01
www.icst.com/products/hiperclocks.html
2
REV. B MARCH 5, 2003
Integrated Circuit Systems, Inc.
ICS8634-01
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER
4.6V -0.5V to VCC + 0.5 V -0.5V to VCCO + 0.5V 47.9°C/W (0 lfpm) -65°C to 150°C N O T E : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 150 15 Units V V V mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter VIH VIL IIH Input High Voltage Input Low Voltage Input High Current SEL0, SEL1, CLK_SEL, MR PLL_SEL IIL Input Low Current SEL0, SEL1, CLK_SEL, MR PLL_SEL VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 5 Units V V µA µA µA µA
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 0.15 1.3 Minimum Typical Maximum 150 5 Units µA µA µA µA V V
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 VCC - 0.85 NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
8634BY-01
www.icst.com/products/hiperclocks.html
3
REV. B MARCH 5, 2003
Integrated Circuit Systems, Inc.
ICS8634-01
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER
Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 1.0 VCCO - 1.7 1.0 Units V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol fIN Parameter Input Frequency CLK0, nCLK0, CLK1, nCLK1 Test Conditions PLL_SEL = 1 PLL_SEL = 0 Minimum 31.25 Typical Maximum 700 700 Units MHz MHz
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 PLL Reference Zero Delay; NOTE 2, 4 Output Skew; NOTE 3, 4 Cycle-to-Cycle Jitter; NOTE 4, 6 Phase Jitter; NOTE 4, 5, 6 PLL Lock Time Output Rise/Fall Time 20% to 80% @ 50MHz 300 PLL_SEL = 0V, f 700MHz PLL_SEL = 3.3V 3.6 -50 3.9 50 Test Conditions Minimum Typical Maximum 700 4.2 150 25 25 ±50 1 700 Units MHz ns ps ps ps ps ms ps %
t(Ø) t sk(o) t jit(cc) t jit()
tL tR / tF
odc Output Duty Cycle 47 53 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Phase jitter is dependent on the input source used. NOTE 6: Characterized at VCO frequency of 622MHz.
8634BY-01
www.icst.com/products/hiperclocks.html
4
REV. B MARCH 5, 2003
Integrated Circuit Systems, Inc.
ICS8634-01
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
VCC , VCCA , VCCO = 2V V CC
Qx
SCOPE
LVPECL
nQx
nCLK0, nCLK1 V CLK0, CLK1 VEE
PP
Cross Points
V
CMR
VEE = -1.3V ± 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
t sk(o)
nQ0:nQ4 Q0:Q4
tcycle
n
t jit(cc) = tcycle n tcycle n+1
1000 Cycles
OUTPUT SKEW
80% 80% V 20% Clock Outputs t
R SW I N G
CYCLE-TO-CYCLE JITTER
nQ0:nQ4 Q0:Q4
Pulse Width t
PERIOD
20% t
F
odc =
t PW t PERIOD
OUTPUT RISE/FALL TIME
odc & tPERIOD
nCLK0, nCLK1
nCLK0, nCLK1 CLK0, CLK1 nQ0:nQ4 Q0:Q4
tP D
CLK0, CLK1 nFB_IN FB_IN
t (Ø)
tjit(Ø) = t(Ø) -- t(Ø) mean = Phase Jitter t (Ø) mean = Static Phase Offset
(where t (Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges)
PROPAGATION DELAY
8634BY-01
PHASE JITTER & STATIC PHASE OFFSET
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5
REV. B MARCH 5, 2003
tcycle n+1
VOH VOL VOH VOL
Others parts begin by 86
86-1
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