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Part: 8701CYI
Category:
Timing Circuits
-> Clock Buffers
Description:
Company: Integrated Circuit System
Datasheet: Download 8701CYI datasheet File size : 27 kB
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Datasheet text preview:
Integrated Circuit Systems, Inc.
LOW SKEW, ÷1, ÷2 CLOCK GENERATOR
FEATURES
· 20 LVCMOS outputs, 7 typical output impedance · LVCMOS / LVTTL clock input · Maximum input frequency: 250MHz · Bank enable logic allows unused banks to be disabled in reduced fanout applications · Bank skew: 200ps · Output skew: 250ps · Multiple frequency skew: 300ps · Part-to-part skew: 600ps · 3.3V or mixed 3.3V input, 2.5V output operating supply · -40°C to 85°C ambient operating temperature · Other divide values available on request
ICS8701I
GENERAL DESCRIPTION
he ICS8701I is a low skew, ÷1, ÷2 Clock Generator and a member of the HiPerClockSTM family H iPer Cl ockSTM o f High Performance Clock Solutions from ICS. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines.
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T h e divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The bank enable inputs, BANK_EN0:1, support enabling and disabling each bank of outputs individually. The master reset input, nMR/OE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. The ICS8701I is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output and part-to-part skew characteristics make the ICS8701I ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK ÷1 ÷2 DIV_SELA 1 QB0:QB4 0 DIV_SELB 1 QC0:QC4 0 DIV_SELC 1 QD0:QD4 0 DIV_SELD nMR/OE BANK_EN0 BANK_EN1 Bank Enable Logic 1 QA0:QA4 0
PIN ASSIGNMENT
GND QB2 GND QB3 VDDO QB4 QC0 VDDO QC1 GND QC2 GND
QC3 VD D O QC4 QD0 VD D O QD1 GND QD2 GND QD3 VD D O QD4
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
ICS8701I
QB1 VDDO QB0 QA4 VDDO QA3 GND QA2 GND QA1 VDDO QA0
48-Pin LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
8701CYI
www.icst.com/products/hiperclocks.html
1
DIV_SELA DIV_SELB CLK GND VD D I BANK_EN0 GND BANK_EN1 VD D I nMR/OE DIV_SELC DIV_SELD
REV. A AUGUST 19, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, ÷1, ÷2 CLOCK GENERATOR
Type Power Description Output supply pins.
ICS8701I
TABLE 1. PIN DESCRIPTIONS
Number 2, 5, 11, 26, 32, 35, 41, 44 7, 9, 18, 21, 28, 30, 37, 39, 46, 48 16, 20 25, 27, 29, 31, 33 34, 36, 38, 40, 42 43, 45, 47, 1, 3 4, 6, 8, 10, 12 22 Name VDDO
GND VDD QA0, QA1, QA2, QA3, QA4 QB0, QB1, QB2, QB3, QB4 QC0, QC1, QC2, QC3, QC4 QD0, QD1, QD2, QD3, QD4 CLK
Power Power
Power supply ground.
Positive supply pins. Bank A outputs.LVCMOS / LVTTLinterface levels. Output 7 typical output impedance. Bank B outputs.LVCMOS / LVTTLinterface levels. Output 7 typical output impedance. Bank C outputs.LVCMOS / LVTTLinterface levels. Output 7 typical output impedance. Bank D outputs. LVCMOS / LVTTLinterface levels. Output 7 typical output impedance. Input Pulldown LVCMOS / LVTTL clock input. Controls frequency division for Bank D outputs. 13 DIV_SELD Input Pullup LVCMOS / LVTTLinterface levels. Controls frequency division for Bank C outputs. 14 DIV_SELC Input Pullup LVCMOS / LVTTLinterface levels. Controls frequency division for Bank B outputs. 23 DIV_SELB Input Pullup LVCMOS / LVTTLinterface levels. Controls frequency division for Bank A outputs. 24 DIV_SELA Input Pullup LVCMOS / LVTTLinterface levels. BANK_EN1, Enables and disables outputs by banks. Input Pullup 17, 19 BANK_EN0 LVCMOS / LVTTLinterface levels. Master Reset and output enable. When HIGH, output drivers are 15 nMR/OE Input Pullup enabled. Whe LOW, output drivers are in HiZ and dividers are reset. LVCMOS / LVTTLinterface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8701CYI
www.icst.com/products/hiperclocks.html
2
REV. A AUGUST 19, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, ÷1, ÷2 CLOCK GENERATOR
Test Conditions Minimum Typical 51 51 VDD, VDDO = 3.465V 7 15 Maximum 4 Units pF K K pF
ICS8701I
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance
TABLE 3. FUNCTION TABLE
nMR/OE 0 1 1 1 1 1 1 1 1 Inputs BANK_EN1 BANK_EN0 X X 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 DIV_SELx X 0 0 0 0 1 1 1 1 QA0:QA4 Hi Z Active Active Active Active Active Active Active Active QB0:QB4 Hi Z Hi Z Active Active Active Hi Z Active Active Active Outputs QC0:QC4 Hi Z Hi Z Hi Z Active Active Hi Z Hi Z Active Active QD0:QD4 Hi Z Hi Z Hi Z Hi Z Active Hi Z Hi Z Hi Z Active Qx frequency zero fIN/2 fIN/2 fIN/2 fIN/2 fIN fIN fIN fIN
8701CYI
www.icst.com/products/hiperclocks.html
3
REV. A AUGUST 19, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, ÷1, ÷2 CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V -40°C to 85°C -65°C to 150°C
ICS8701I
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Inputs Outputs Ambient Operating Temperature Storage Temperature
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol V DD VDDO IDD Parameter Positive Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 100 Units V V mA
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Input High Voltage DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK Test Conditions Minimum 2 2 -0.3 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V VDD = VDDO = 3.135V IOH = -36mA VDD = VDDO = 3.135V IOL = 36mA -150 -5 2.6 0.5 Typical Maximum 3.8 3.8 0.8 1.3 5 150 Units V V V V µA µA µA µA V V
VIH
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
VOH VOL
Output High Voltage Output Low Voltage
8701CYI
www.icst.com/products/hiperclocks.html
4
REV. A AUGUST 19, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, ÷1, ÷2 CLOCK GENERATOR
Test Conditions 0MHz f 200MHz 0MHz f 200MHz Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 30% to 70% 30% to 70% 0MHz f 200MHz f = 200MHz 200 200 tCYCLE/2 - 0.6 1.9 tCYCLE/2 2.5 Minimum Typical Maximum 250 2.2 2.2 3.6 3.6 200 250 300 600 900 900 tCYCLE/2 + 0.6 3.1 Units MHz ns ns ps ps ps ps ps ps ns ns ns ns
ICS8701I
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol fMAX tpLH tpHL Parameter Input Frequency Propagation Delay, Low-to-High; NOTE 1 Propagation Delay, High-to-Low; NOTE 1 Bank Skew; NOTE 2, 7 Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t to Par t Skew; NOTE 5, 7 Output Rise Time; NOTE 6 Output Fall Time; NOTE 6 Output Pulse Width
tsk(b) tsk(o) tsk(w) tsk(pp)
tR tF tPW tEN
Output Enable Time; f = 10MHz 6 NOTE 6 Output Disable Time; tDIS f = 10MHz 6 NOTE 6 All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the VDD input crossing point to the output at VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions. NOTE 4 Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
8701CYI
www.icst.com/products/hiperclocks.html
5
REV. A AUGUST 19, 2002
Others parts begin by 87
87-1 87-2
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