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Details, datasheet, quote on part number:8725AY-01
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Integrated Circuit Systems, Inc.
ICS8725-01
1:5 DIFFERENTIAL-TO-LVHSTL ZERO DELAY CLOCK GENERATOR
FEATURES
· 5 differential LVHSTL outputs · Selectable differential CLKx, nCLKx input pairs · CLKx, nCLKx pairs can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL · Output frequency range: 31.25MHz - 700MHz · Input frequency range: 31.25MHz - 700MHz · VCO range: 250MHz - 700MHz · External feedback for "zero delay" clock regeneration with configurable frequencies · Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 · Static phase offset: ±100ps · Cycle-to-cycle jitter: 25ps · Output skew: 25ps · 3.3V core, 1.8V output operating supply · 0°C to 70°C ambient operating temperature · Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8725-01 is a highly versatile 1:5 Differential-to-LVHSTL clock generator and a member H iPerC lockSTM of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8725-01 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.
,&6
BLOCK DIAGRAM
PLL_SEL Q0 nQ0 Q1 nQ1 0 Q2 nQ2 1 CLK1 nCLK1 CLK_SEL FB_IN nFB_IN 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 1 Q3 nQ3
PIN ASSIGNMENT
PLL_SEL SEL3 GND VDDO
VDDA
nQ4
VDD
Q4
CLK0 nCLK0
÷1, ÷2, ÷4, ÷8, ÷16, ÷32, ÷64 0
32 31 30 29 28 27 26 25 SEL0 SEL1 CLK0 nCLK0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VDD nFB_IN FB_IN SEL2 GND nQ0 Q0 VDDO
24 23 22
VDDO Q3 nQ3 Q2 nQ2 Q1 nQ1 VDDO
PLL
Q4 nQ4
CLK1 nCLK1 CLK_SEL MR
ICS8725-01
21 20 19 18 17
SEL0 SEL1 SEL2 SEL3 MR
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
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1
REV. A NOVEMBER 20, 2001
8725AY-01
Integrated Circuit Systems, Inc.
ICS8725-01
1:5 DIFFERENTIAL-TO-LVHSTL ZERO DELAY CLOCK GENERATOR
Type Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8 9, 32 10 11 12 13, 28 14, 15 16, 17, 24, 25 18, 19 20, 21 22, 23 26, 27 29 30 31 Name SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL MR VDD nFB_IN FB_IN SEL2 GND nQ0, Q0 VDDO nQ1, Q1 nQ2, Q2 nQ3, Q3 nQ4, Q4 SEL3 VDDA PLL_SEL Input Input Input Input Input Input Input Input Power Input Input Input Power Output Power Output Output Output Output Input Power Input Pullup Pullup Pulldown Determines output divider values in Table 3. LVCMOS interface levels. Pulldown Determines output divider values in Table 3. LVCMOS interface levels. Pulldown Non-inver ting differential clock input. Pullup Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When HIGH, selects CLK1, nCLK1. Pulldown When LOW, selects CLK0, nCLK0. LVCMOS interface levels. Pulldown Master reset. Resets the output divider. LVCMOS interface levels. Positive supply pins. Connect to 3.3V. Feedback input to phase detector for regenerating clocks with "zero delay". Pulldown Feedback input to phase detector for regenerating clocks with "zero delay". Pulldown Determines output divider values in Table 3. LVCMOS interface levels. Power supply ground. Connect to ground. Differential output pair. LVHSTL interface levels. Output supply pins. Connect to 1.8V. Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels. Pulldown Determines output divider values in Table 3. LVCMOS interface levels. Analog supply pin. Connect to 3.3V. Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
8725AY-01
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REV. A NOVEMBER 20, 2001
Integrated Circuit Systems, Inc.
ICS8725-01
1:5 DIFFERENTIAL-TO-LVHSTL ZERO DELAY CLOCK GENERATOR
Outputs PLL_SEL = 1 PLL Enable Mode Q0 - Q4, nQ0 - nQ4 ÷1 ÷1 ÷1 ÷1 ÷2 ÷2 ÷2 ÷4 ÷4 ÷8 x2 x2 x2 x4 x4 x8
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference Frequency Range (MHz)* 250 - 700 125 - 350 62.5 - 175 31.25 - 87.5 250 - 700 125 - 350 62.5 - 175 250 - 700 125 - 350 250 - 700 125 - 350 62.5 - 175 31.25 - 87.5 62.5 - 175 31.25 - 87.5 31.25 - 87.5
*NOTE: VCO frequency range for all configurations above is 250 to 700MHz.
TABLE 3B. PLL BYPASS FUNCTION TABLE
Inputs S EL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
8725AY-01
SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Outputs PLL_SEL = 0 PLL Bypass Mode Q0 - Q4, nQ0 - nQ4 ÷4 ÷4 ÷4 ÷8 ÷8 ÷8 ÷ 16 ÷ 16 ÷ 32 ÷ 64 ÷2 ÷2 ÷4 ÷1 ÷2 ÷1
REV. A NOVEMBER 20, 2001
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3
Integrated Circuit Systems, Inc.
ICS8725-01
1:5 DIFFERENTIAL-TO-LVHSTL ZERO DELAY CLOCK GENERATOR
4.6V -0.5V to VDD+0.5 V -0.5V to VDDO+0.5V 47.9°C/W (0 lfpm) -65°C to 150°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Positive Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current No Load 0 Test Conditions Minimum 3.135 3.135 1.6 Typical 3.3 3.3 1.8 Maximum 3.465 3.465 2.0 120 15 Units V V V mA mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage CLK_SEL, MR, SEL0, SEL1, SEL2, SEL3 PLL_SEL CLK_SEL, MR, SEL0, SEL1, SEL2, SEL3 PLL_SEL *NOTE: VDDx denotes VDD and VDDA. *VDDx = VIN = 3.465V VDDO = 2V *VDDx = VIN = 3.465V VDDO = 2V *VDDx = 3.465V, VDDO = 2V, VIN = 0V *VDDx = 3.465V, VDDO = 2V, VIN = 0V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 5 Units V V µA µA µA µA
Input High Current
IIL
Input Low Current
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter IIH IIL VPP Input High Current Input Low Current CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN Test Conditions *VDDx = VIN = 3.465V *VDDx = VIN = 3.465V *VDDx = 3.465V, VIN = 0V *VDDx = 3.465V, VIN = 0V -5 -150 0.15 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units µA µA µA µA V V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 0.5 VCMR NOTE 1: For single ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. *NOTE: VDDx denotes VDD and VDDA.
8725AY-01
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4
REV. A NOVEMBER 20, 2001
Integrated Circuit Systems, Inc.
ICS8725-01
1:5 DIFFERENTIAL-TO-LVHSTL ZERO DELAY CLOCK GENERATOR
Test Conditions Minimum 1 0 40% x (VOH - VOL) + VOL 0.6 Typical Maximum 1.4 0.4 60% x (VOH - VOL) + VOL 1.1 Units V V V V
TABLE 4D. LVHSTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter Output High Voltage; VOH NOTE 1 Output Low Voltage; VOL NOTE 1 VOX Output Crossover Voltage
Peak-to-Peak VSWING Output Voltage Swing NOTE 1: Outputs terminated with 50 to ground.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol fIN Parameter Input Frequency CLK0, nCLK0, CLK1, nCLK1 Test Conditions PLL_SEL = 1 PLL_SEL = 0 Minimum 31.25 Typical Maximum 700 700 Units MHz MHz
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol fMAX tPD t(Ø) t sk(o) t jit(cc) t jit(Ø) tL tR tF Parameter Output Frequency Propagation Delay; NOTE 1 Static Phase Offset; NOTE 2, 5 Output Skew; NOTE 3, 5 Cycle-to-Cycle Jitter; NOTE 5, 6 Phase Jitter; NOTE 4, 5, 6 PLL Lock Time Output Rise Time Output Fall Time 20% to 80% @ 50MHz 20% to 80% @ 50MHz 300 300 PLL_SEL = 0V 700MHz PLL_SEL = 3.3V 3.4 -100 3.9 Test Conditions Minimum Typical Maximum 700 4.4 100 25 25 ±50 1 700 700 Units MHz ns ps ps ps ps ms ps ps ps
tPW Output Pulse Width tcycle/2 - 85 tcycle/2 tcycle/2 + 85 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal across alll conditions, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Characterized at VCO frequency of 622MHz.
8725AY-01
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REV. A NOVEMBER 20, 2001
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