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Part: 8735AY-01
Category:
Timing Circuits
-> Clock Buffers
Description:
Company: Integrated Circuit System
Datasheet: Download 8735AY-01 datasheet File size : 1002 kB
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Integrated Circuit Systems, Inc.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
FEATURES
· 5 differential 3.3V LVPECL outputs · Selectable differential clock inputs · CLKx, nCLKx pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL · Output frequency range: 31.25MHz to 700MHz · Input frequency range: 31.25MHz to 700MHz · VCO range: 250MHz to 700MHz · Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 · External feedback for "zero delay" clock regeneration with configurable frequencies · Cycle-to-cycle jitter: 25ps (maximum) · Output skew: 25ps (maximum) · Static phase offset: 50ps ± 100ps · 3.3V supply voltage · 0°C to 70°C ambient operating temperature · Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8735-01 is a highly versatile 1:5 Differential-to-3.3V LVPECL clock generator and a H iPerC lockSTM member of the HiPerClockSTM family of High P e r f o r m a n c e Clock Solutions from ICS. The ICS8735-01 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-toinput frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.
,&6
BLOCK DIAGRAM
PLL_SEL
÷1, ÷2, ÷4, ÷8, ÷16, ÷32, ÷64
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 Q2 nQ2 1 SEL0 Q3 nQ3 SEL1 CLK0 Q4 nQ4 nCLK0 CLK1 nCLK1 CLK_SEL MR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VCC PLL_SEL SEL3
VCCO
VCCA
nQ4
VEE
Q4
0
CLK0 nCLK0 CLK1 nCLK1 CLK_SEL FB_IN nFB_IN
0 1
32 31 30 29 28 27 26 25 24 23 22 V CCO Q3 nQ3 Q2 nQ2 Q1 nQ1 V CCO
PLL
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
ICS8735-01
21 20 19 18 17
SEL0 SEL1 SEL2 SEL3 MR
32-Lead QFP (LQFP) 7mm x 7mm x 1.4mm package body Y Package Top View
VCC
nFB_IN
FB_IN
SEL2
VEE
nQ0
Q0
VCCO
8735AY-01
www.icst.com/products/hiperclocks.html
1
REV. E JANUARY 31, 2003
Integrated Circuit Systems, Inc.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 Name SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL Input Input Input Input Input Input Input Type Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When HIGH, selects CLK1, nCLK1. Pulldown When LOW, selects CLK0, nCLK0. LVCMOS / LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx to go high. Pulldown When logic LOW, the internal dividers and the otuputs are enabled. LVCMOS / LVTTL interface levels. Core supply pins. Pullup Feedback input to phase detector for regenerating clocks with "zero delay". Pulldown Feedback input to phase detector for regenerating clocks with "zero delay". Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Negative supply pins. Differential output pair. LVPECL interface levels. Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Analog supply pin. Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock.When HIGH, selects PLL. LVCMOS / LVTTL interface levels.
8 9, 32 10 11 12 13, 28 14, 15 16, 17, 24, 25 18, 19 20, 21 22, 23 26, 27 29 30 31
MR VCC nFB_IN FB_IN SEL2 VEE nQ0, Q0 VCCO nQ1, Q1 nQ2, Q2 nQ3, Q3 nQ4, Q4 SEL3 VCCA PLL_SEL
Input Power Input Input Input Power Output Power Output Output Output Output Input Power Input
Pullup
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
8735AY-01
www.icst.com/products/hiperclocks.html
2
REV. E JANUARY 31, 2003
Integrated Circuit Systems, Inc.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Outputs PLL_SEL = 1 PLL Enable Mode Q0:Q4, nQ0:nQ4 ÷1 ÷1 ÷1 ÷1 ÷2 ÷2 ÷2 ÷4 ÷4 ÷8 x2 x2 x2 x4 x4 x8
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference Frequency Range (MHz)* 250 - 700 125 - 350 62.5 - 175 31.25 - 87.5 250 - 700 125 - 350 62.5 - 175 250 - 700 125 - 350 250 - 700 125 - 350 62.5 - 175 31.25 - 87.5 62.5 - 175 31.25 - 87.5 31.25 - 87.5
*NOTE: VCO frequency range for all configurations above is 250 to 700MHz.
TABLE 3B. PLL BYPASS FUNCTION TABLE
Inputs S EL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
8735AY-01
SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Outputs PLL_SEL = 0 PLL Bypass Mode Q0:Q4, nQ0:nQ4 ÷4 ÷4 ÷4 ÷8 ÷8 ÷8 ÷ 16 ÷ 16 ÷ 32 ÷ 64 ÷2 ÷2 ÷4 ÷1 ÷2 ÷1
REV. E JANUARY 31, 2003
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3
Integrated Circuit Systems, Inc.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
4.6V -0.5V to VCC + 0.5 V -0.5V to VCCO + 0.5V 47.9°C/W (0 lfpm) -65°C to 150°C N O T E : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter VCC VCCA VCCO IEE ICCA Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 150 15 Units V V V mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter VIH VIL IIH Input High Voltage Input Low Voltage Input High Current CLK_SEL, MR, SEL0, SEL1, SEL2, SEL3 PLL_SEL CLK_SEL, MR, SEL0, SEL1, SEL2, SEL3 PLL_SEL VIN = VCC = 3.465V VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 5 Units V V µA µA µA µA
IIL
Input Low Current
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter IIH IIL VPP Input High Current Input Low Current CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN Test Conditions VIN = VCC = 3.465V VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -5 -150 0.15 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units µA µA µA µA V V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 VCMR NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
8735AY-01
www.icst.com/products/hiperclocks.html
4
REV. E JANUARY 31, 2003
Integrated Circuit Systems, Inc.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 1.0 VCCO - 1.7 1.0 Units V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol fIN Parameter Input Frequency CLK0, nCLK0, CLK1, nCLK1 Test Conditions PLL_SEL = 1 PLL_SEL = 0 Minimum 31.25 Typical Maximum 700 700 Units MHz MHz
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol fMAX tPD t(Ø) t sk(o) t jit(cc) t jit() tL tR tF Parameter Output Frequency Propagation Delay; NOTE 1 Static Phase Offset; NOTE 2, 5 Output Skew; NOTE 3, 5 Cycle-to-Cycle Jitter; NOTE 5, 6 Phase Jitter; NOTE 4, 5, 6 PLL Lock Time Output Rise Time Output Fall Time 20% to 80% @ 50MHz 20% to 80% @ 50MHz 300 300 PLL_SEL = 0V, f 700MHz PLL_SEL = 3.3V 3.4 -50 50 Test Conditions Minimum Typical Maximum 700 4.2 150 25 25 ±50 1 700 700 Units MHz ns ps ps ps ps ms ps ps %
odc Output Duty Cycle 47 53 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Characterized at VCO frequency of 622MHz.
8735AY-01
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REV. E JANUARY 31, 2003
Others parts begin by 87
87-1 87-2
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