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Details, datasheet, quote on part number:8737AG-11
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Datasheet text preview:
Integrated Circuit Systems, Inc.
LOW SKEW, ¸1/¸2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
FEATURES
· 2 divide by 1 differential 3.3V LVPECL outputs; 2 divide by 2 differential 3.3V LVPECL outputs · Selectable differential CLK, nCLK or LVPECL clock inputs · CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL · PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL · Maximum output frequency: 650MHz · Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input · Output skew: 60ps (maximum) · Part-to-part skew: 200ps (maximum) · Bank skew: Bank A - 20ps (maximum), Bank B - 35ps (maximum) · Propagation delay: 1.7ns (maximum) · 3.3V operating supply · 0°C to 70°C ambient operating temperature · Industrial temperature information available upon request
ICS8737-11
GENERAL DESCRIPTION
The ICS8737-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/ H iPerC lockSTM D i v i d e r and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8737-11 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differe n t i a l input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.The clock enable is i n t e r n a l l y synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
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G u a r a n t e e d output and part-to-part skew characteristics make the ICS8737-11 ideal for clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
QA0 nQA0 CLK_EN D Q LE CLK nCLK PCLK nPCLK CLK_SEL MR 0 1 ÷1 ÷2 QB0 nQB0 QB1 nQB1 QA1 nQA1
PIN ASSIGNMENT
VEE CLK_EN CLK_SEL CLK nCLK PCLK nPCLK nc MR VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 QA0 nQA0 VCC QA1 nQA1 QB0 nQB0 VCC QB1 nQB1
ICS8737-11
20-Lead TSSOP 6.50mm x 4.40mm x 0.92 package body G Package Top View
8737AG-11
www.icst.com/products/hiperclocks.html
1
REV. A JUNE 3, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, ¸1/¸2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
Type Description
ICS8737-11
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 Name VEE CLK_EN CLK_SEL CLK Power Power Input Input Negative supply pin. Synchronizing clock enable. When HIGH, clock outputs follow clock input. Pullup When LOW, Q outputs are forced low, nQ outputs are forced high. LVTTL / LVCMOS interface levels. Clock Select input. When HIGH, selects PCLK, nPCLK inputs. Pulldown When LOW, selects CLK, nCLK inputs. LVTTL / LVCMOS interface levels. Pulldown Non-inver ting differential clock input.
5 nCLK Input Pullup Inver ting differential clock input. 6 PCLK Input Pulldown Non-inver ting differential LVPECL clock input. 7 nPCLK Input Pullup Inver ting differential LVPECL clock input. 8 nc Unused No connect. 9 MR Input Pulldown Master reset. Resets the output divider. LVTTL / LVCMOS interface levels. Power Positive supply pins. 10, 13, 18 VCC 11, 12 nQB1, QB1 Output Differential output pair. LVPECL interface levels. 14, 15 nQB0, QB0 Output Differential output pair. LVPECL interface levels. 16, 17 nQA1, QA1 Output Differential output pair. LVPECL interface levels. 19, 20 nQA0, QA0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
8737AG-11
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2
REV. A JUNE 3, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, ¸1/¸2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
Outputs
ICS8737-11
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs MR 1 0 0 0 CLK_EN X 0 0 1 CLK_SEL X 0 1 0 Selected Source X CLK, nCLK PCLK, nPCLK CLK, nCLK QA0, QA1 LOW Disabled; LOW Disabled; LOW Enabled HIGH Disabled; HIGH Disabled; HIGH Enabled nQA0, nQA1 QB0, QB1 LOW Disabled; LOW Disabled; LOW Enabled nQB0, nQB1 HIGH Disabled; HIGH Disabled; HIGH Enabled
0 1 1 PCLK, nPCLK Enabled Enabled Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown if Figure 1. In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described in Table 3B.
Disabled
Enabled
nCLK, nPCLK CLK, PCLK
CLK_EN
nQA0, nQA1, nQB0, nQB1 QA0, QA1, QB0, QB1
FIGURE 1 - CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK or PCLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK or nPCLK 0 1 Biased; NOTE 1 Biased; NOTE 1 0 1 QAx LOW HIGH LOW HIGH HIGH LOW Outputs nQAx HIGH LOW HIGH LOW LOW HIGH QBx LOW HIGH LOW HIGH HIGH LOW nQBx HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
8737AG-11
www.icst.com/products/hiperclocks.html
3
REV. A JUNE 3, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, ¸1/¸2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
4.6V -0.5V to VCC + 0.5V -0.5V to VCC + 0.5V 73.2°C/W (0 lfpm) -65°C to 150°C
ICS8737-11
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, V I Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 50 Units V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol VIH VIL IIH IIL Parameter CLK_EN, CLK_SEL, MR CLK_EN, CLK_SEL, MR Input High Current Input Low Current CLK_EN CLK_SEL, MR CLK_EN CLK_SEL,MR VIN = VCC = 3.465V VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -150 -5 Test Conditions Minimum 2 -0.3 Typical Maximum 3.765 0.8 5 150 Units V V µA µA µA µA
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK CLK nCLK CLK Test Conditions VIN = VCC = 3.465V VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -150 -5 1.3 VCC - 0.85 Minimum Typical Maximum 5 150 Units µA µA µA µA V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
8737AG-11
www.icst.com/products/hiperclocks.html
4
REV. A JUNE 3, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, ¸1/¸2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
Test Conditions VIN = VCC = 3.465V VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -5 -150 0.3 VEE + 1.5 VCC - 1.4 VCC - 2.0 1 VCC VCC - 1.0 VCC - 1.7 0.9 Minimum Typical Maximum 150 5 Units µA µA µA µA V V V V V
ICS8737-11
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter IIH IIL VPP VCMR VOH VOL Input High Current Input Low Current Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Output High Voltage; NOTE 3 Output Low Voltage; NOTE 3
VSWING Peak-to-Peak Output Voltage Swing 0.65 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. NOTE 3: Outputs terminated with 50 to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter fMAX tPD Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Bank Skew; NOTE 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time 20% to 80% @ 50MHz 20% to 80% @ 50MHz 300 300 Bank A Bank B CLK, nCLK PCLK, nPCLK 650MHz 1.3 1.2 Test Conditions Minimum Typical Maximum 650 1.7 1.6 60 20 35 200 700 700 52 Units MHz ns ns ps ps ps ps ps ps %
t sk(o) t sk(b) t sk(pp)
tR tF
odc Output Duty Cycle 48 50 All parameters measured at 500MHz unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8737AG-11
www.icst.com/products/hiperclocks.html
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REV. A JUNE 3, 2002
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