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Details, datasheet, quote on part number:8745AY
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Integrated Circuit Systems, Inc.
ICS8745
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
FEATURES
· 5 differential LVDS outputs designed to meet or exceed the requirements of ANSI TIA/EIA-644 · Selectable differential clock inputs · CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL · Output frequency range: 31.25MHz to 700MHz · Input frequency range: 31.25MHz to 700MHz · VCO range: 250MHz to 700MHz · External feedback for "zero delay" clock regeneration with configurable frequencies · Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 · Cycle-to-cycle jitter: 25ps (maximum) · Output skew: 35ps (maximum) · Static phase offset: 50ps ± 150ps · 3.3V supply voltage · 0°C to 70°C ambient operating temperature · Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8745 is a highly versatile 1:5 LVDS Clock Generator and a member of the HiPerClockSTM H iPer Cl ockSTM family of High Performance Clock Solutions from ICS. The ICS8745 has a fully integrated PLL and can be configured as zero delay buffer, multip l i e r or divider, and has an output frequency range of 31.25MHz to 700MHz. The Reference Divider, Feedback Divider and Output Divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.
,&6
BLOCK DIAGRAM
PLL_SEL ÷1, ÷2, ÷4, ÷8, ÷16, ÷32, ÷64 0 1 CLK1 nCLK1 CLK_SEL FB_IN nFB_IN 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 1 0
PIN ASSIGNMENT
Q0 nQ0
VDD PLL_SEL SEL3 GND VD D O
VDDA
nQ4
Q1 nQ1 Q2 nQ2 Q3 nQ3
Q4
CLK0 nCLK0
32 31 30 29 28 27 26 25 SEL0 SEL1 CLK0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VDD nFB_IN FB_IN SEL2 GND nQ0 Q0 VD D O
24 23 22
Q3 nQ3 VD D O Q2 nQ2 GND Q1 nQ1
PLL
Q4 nQ4
nCLK0 CLK1 nCLK1 CLK_SEL MR
ICS8745
21 20 19 18 17
SEL0 SEL1 SEL2 SEL3 MR
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
8745AY
www.icst.com/products/hiperclocks.html
1
REV. D FEBRUARY 12, 2003
Integrated Circuit Systems, Inc.
ICS8745
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Type Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 Name SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL Input Input Input Input Input Input Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When HIGH, selects CLK1, nCLK1. Pulldown When LOW, selects CLK0, nCLK0. LVCMOS / LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx to go Pulldown high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Core supply pins. Pullup Feedback input to phase detector for regenerating clocks with "zero delay". Pulldown Feedback input to phase detector for regenerating clocks with "zero delay". Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Power supply ground. Differential output pair. LVDS interface levels. Output supply pins. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Analog supply pin. Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
8 9, 32 10 11 12 13, 19, 25 14, 15 16, 22, 28 17, 18 20, 21 23, 24 26, 27 29 30 31
MR VDD nFB_IN FB_IN SEL2 GND nQ0, Q0 VDDO nQ1, Q1 nQ2, Q2 nQ3, Q3 nQ4, Q4 SEL3 VDDA PLL_SEL
Input Power Input Input Input Power Output Power Output Output Output Output Input Power Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
8745AY
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REV. D FEBRUARY 12, 2003
Integrated Circuit Systems, Inc.
ICS8745
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Outputs PLL_SEL = 1 PLL Enable Mode Q0:Q4, nQ0:nQ4 ÷1 ÷1 ÷1 ÷1 ÷2 ÷2 ÷2 ÷4 ÷4 ÷8 x2 x2 x2 x4 x4 x8
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference Frequency Range (MHz)* 250 - 700 125 - 350 62.5 - 175 31.25 - 87.5 250 - 700 125 - 350 62.5 - 175 250 -700 125 - 350 250 - 700 125 - 350 62.5 - 175 31.25 - 87.5 62.5 - 175 31.25 - 87.5 31.25 - 87.5
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
TABLE 3B. PLL BYPASS FUNCTION TABLE
Inputs S EL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
8745AY
SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Outputs PLL_SEL = 0 PLL Bypass Mode Q0:Q4, nQ0:nQ4 ÷4 ÷4 ÷4 ÷8 ÷8 ÷8 ÷ 16 ÷ 16 ÷ 32 ÷ 64 ÷2 ÷2 ÷4 ÷1 ÷2 ÷1
REV. D FEBRUARY 12, 2003
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Integrated Circuit Systems, Inc.
ICS8745
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9°C/W (0 lfpm) -65°C to 150°C N O T E : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 80 15 20 Units V V V mA mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter VIH VIL IIH Input High Voltage Input Low Voltage Input High Current CLK_SEL, MR, SEL0, SEL1, SEL2, SEL3 PLL_SEL CLK_SEL, MR, SEL0, SEL1, SEL2, SEL3 PLL_SEL VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 5 Units V V µA µA µA µA
IIL
Input Low Current
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter IIH IIL VPP VCMR Input High Current Input Low Current CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.15 GND + 0.5 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units µA µA µA µA V V
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2
NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V.
8745AY
www.icst.com/products/hiperclocks.html
4
REV. D FEBRUARY 12, 2003
Integrated Circuit Systems, Inc.
ICS8745
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Test Conditions Minimum 230 1.125 Typical 350 0 1.25 5 -3.5 -3.5 -20 0.9 ±1 1.34 1.06 +20 1.6 Maximum 460 40 1.375 25 Units mV mV V mV mA mA µA V V
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol VOD VOD VOS VOS IOSD IOs IOFF VOH VOL Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Differential Output Shor t Circuit Current Output Shor t Circuit Current Power Off Leakage Output Voltage High Output Voltage Low
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol fIN Parameter Input Frequency CLK0, nCLK0, CLK1, nCLK1 Test Conditions PLL_SEL = 1 PLL_SEL = 0 Minimum 31.25 Typical Maximum 700 700 Units MHz MHz
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Static Phase Offset; NOTE 2, 5 Output Skew; NOTE 3, 5 Cycle-to-Cycle Jitter ; NOTE 5, 6 Phase Jitter ; NOTE 4, 5, 6 Output Pulse Width PLL Lock Time Output Rise/Fall Time; NOTE 7 f 155.5MHz 150 tPERIOD/2 - 85 tPERIOD/2 PLL_SEL = 0V, f 700MHz PLL_SEL = 3.3V 4.5 -100 5 50 Test Conditions Minimum Typical Maximum 700 5.5 200 35 25 ±50 tPERIOD/2 + 85 1 550 450 Units MHz ns ps ps ps ps ps ms ps ps
tsk(Ø) tsk(o) tjit(cc) tjit()
tPW tL tR / tF
f > 155.5MHz 50 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Characterized at VCO frequency of 622MHz. NOTE 7: Measured from the 20% to 80% points. Guaranteed by characterization. Not production tested.
8745AY
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REV. D FEBRUARY 12, 2003
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