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Part: 8752BY
Category:
Timing Circuits
-> Clock Buffers
Description:
Company: Integrated Circuit System
Datasheet: Download 8752BY datasheet File size : 813 kB
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Integrated Circuit Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
FEATURES
· Fully integrated PLL · 8 LVCMOS outputs, 7 typical output impedance · Selectable LVCMOS CLK0 or CLK1 inputs for redundant clock applications · Input/Output frequency range: 18.33MHz to 240MHz at VCC = 3.3V ± 5% · VCO range: 220MHz to 480MHz · External feedback for "zero delay" clock regeneration · Cycle-to-cycle jitter: 75ps (maximum), (all outputs are the same frequency) · Output skew: 100ps (maximum) · Bank skew: 55ps (maximum) · 3.3V or 2.5V supply voltage · 0°C to 70°C ambient operating temperature · Industrial temperature information available upon request · Functionally compatible with MPC952 in some applications
GENERAL DESCRIPTION
T h e ICS8752 is a low voltage, low skew LV C M O S clock generator and a member of H iPer Cl ockSTM the HiPerClockSTM family of High Performance C l o c k Solutions from ICS. With output frequencies up to 240MHz, the ICS8752 is targeted for high performance clock applications. Along with a fully integrated PLL, the ICS8752 contains frequency configurable outputs and an external feedback input for regenerating clocks with "zero delay".
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Dual clock inputs, CLK0 and CLK1, support redundant clock applications. The CLK_SEL input determines which reference clock is used. The output divider values of Bank A and B are controlled by the DIV_SELA0:1, and DIV_SELB0:1, respectively. For test and system debug purposes, the PLL_SEL input allows the PLL to be bypassed. When HIGH, the MR/nOE input resets the internal dividers and forces the outputs to the high impedance state. The low impedance LVCMOS outputs of the ICS8752 are designed to drive terminated transmission lines. The effective fanout of each output can be doubled by utilizing the ability of each output to drive two series terminated transmission lines.
BLOCK DIAGRAM
PLL_SEL PLL FB_IN CLK0 0 CLK1 1 CLK_SEL DIV_SELA1 DIV_SELA0
00 01 10 11 PHASE DETECTOR VCO 1 0 ÷2 ÷4 ÷6 ÷8 ÷12 00 01 10 11
PIN ASSIGNMENT
PLL_SEL GND GND VD D O QB3 QB2 VDD nc
32 31 30 29 28 27 26 25 QA0 QA1 QA2 QA3 DIV_SELB0 DIV_SELB1 DIV_SELA0 DIV_SELA1 MR/nOE CLK0 QB0 QB1 QB2 QB3
CLK_SEL VDDA VD D CLK1 GND QA0 QA1 VD D O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22
GND QB1 QB0 VDDO VDDO QA3 QA2 GND
ICS8752
21 20 19 18 17
GND FB_IN
DIV_SELB1 DIV_SELB0
MR/nOE
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View
8752CY
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1
REV. A AUGUST 19, 2002
Integrated Circuit Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Type Description Determines output divider values for Bank B as described in Table 3. Pulldown LVCMOS / LVTTL interface levels. Determines output divider values for Bank A as described in Table 3. Pulldown LVCMOS / LVTTL interface levels. Active LOW Master Reset and output enable. When logic LOW, the Pulldown internal dividers are reset. When HIGH, the Master Reset is disabled. LVCMOS / LVTTL interface levels. Pulldown Clock input. LVCMOS / LVTTL interface levels. Power supply ground. Pulldown Feedback input to phase detector for generating clocks with "zero delay". LVCMOS / LVTTL interface levels. Clock select input. Selects between CLK0 or CLK1 as phase detector Pulldown reference. When LOW, selects CLK0. When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. Analog supply pin. Positive supply pins. Pulldown Clock input. LVCMOS / LVTTL interface levels. Bank A clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. Output supply pins. Bank B clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. No connect. Pullup Selects between the PLL and CLK0 or CLK1 as the input to the dividers. When HIGH selects PLL. When LOW selects CLK0 or CLK1. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5 6 7, 13, 17, 24, 28, 29 8 9 10 11, 32 12 14, 15, 18, 19 16, 20, 21, 25 22, 23, 26, 27 30 31 Name DIV_SELB0, DIV_SELB1 DIV_SELA0, DIV_SELA1 MR/nOE CLK0 GND FB_IN CLK_SEL VDDA VDD CLK1 QA0, QA1, QA2, QA3 VDDO QB0, QB1, QB2, QB3 nc PLL_SEL
Input Input Input Input Power Input Input Power Power Input Output Power Output Unused Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance 51 51 VDDA, VDD, VDDO = 3.465V 23 7 Test Conditions Minimum Typical Maximum 4 Units pF K K pF
8752CY
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2
REV. A AUGUST 19, 2002
Integrated Circuit Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Inputs DIV_ SELA1 X 0 0 1 1 0 0 1 1 0 0 1 1 Outputs DIV_ SELA0 X 0 1 0 1 0 1 0 1 0 1 0 1 DIV_ SELB1 X 0 0 1 1 0 0 1 1 0 0 1 1 DIV_ SELB0 X 0 1 0 1 0 1 0 1 0 1 0 1 QAx Hi-Z fVCO/2 fVCO/4 fVCO/6 fVCO/8 fCLK0/2 fCLK0/4 fCLK0/6 fCLK0/8 fCLK1/2 fCLK1/4 fCLK1/6 fCLK1/8 QBx Hi-Z fVCO/4 fVCO/6 fVCO/8 fVCO/12 fCLK0/4 fCLK0/6 fCLK0/8 fCLK0/12 fCLK1/4 fCLK1/6 fCLK1/8 fCLK1/12
TABLE 3. CONTROL INPUT FUNCTION TABLE
MR/nOE 1 0 0 0 0 0 0 0 0 0 0 0 0
PLL_SEL X 1 1 1 1 0 0 0 0 0 0 0 0
CLK_SEL X X X X X 0 0 0 0 1 1 1 1
NOTE: For normal operation, MR/nOE is LOW. When MR/nOE is HIGH, all ouputs are disabled.
TABLE 4A. QA OUTPUT FREQUENCY
W/FB_IN
= QB
Inputs Outputs DIV_ SELA1 0 DIV_ SELA0 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 QA Output Divider Mode ÷2 ÷4 ÷6 ÷8 ÷2 ÷4 ÷6 ÷8 ÷2 ÷4 ÷6 ÷8 ÷2 ÷4 ÷6 ÷8 QA Multiplier (NOTE 2) 2 1 0.667 0.5 3 1.5 1 0.75 4 2 1.33 1 6 3 2 1.5
FB_IN
DIV_ DIV_ SELB1 SELB0
QB Output Divider Mode (NOTE 2)
CLK0, CLK1 (MHz) (NOTE 1) Minimum Maximum
QB
0
0
÷4
55
120
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
QB
0
1
÷6
36.66
80
QB
1
0
÷8
27.5
60
QB
1
1
÷12
18.33
40
NOTE 1: VCO frequency range is 220MHz to 480MHz. NOTE 2: QA output frequency equal to CLKx frequency times the multiplier ; QB output frequency equal to CLKx.
8752CY
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3
REV. A AUGUST 19, 2002
Integrated Circuit Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
W/FB_IN
TABLE 4B. QB OUTPUT FREQUENCY
= QA
Inputs CLK0, CLK1 (MHz) (NOTE 1) Minimum Maximum Outputs DIV_ SELB1 0 DIV_ SELB0 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 QB Output Divider Mode ÷4 ÷6 ÷8 ÷12 ÷4 ÷6 ÷8 ÷12 ÷4 ÷6 ÷8 ÷12 ÷4 ÷6 ÷8 ÷12 QB Multiplier (NOTE 2) 0.5 0.333 0.25 0.167 1 0.667 0.5 0.333 1.5 1 0.75 0.5 2 1.333 1 0.667
FB_IN
DIV_ SELA1
DIV_ SELA0
QA Output Divider Mode (NOTE 2) ÷2
QA
0
0
110
240 (NOTE 3)
0 1 1 0 0 1 1 0 0 1 1 0 0 1
QA
0
1
÷4
55
120
QA
1
0
÷6
36.66
80
QA
1
1
÷8
27.5
60
1 NOTE 1: VCO frequency range is 220MHz to 480MHz. NOTE 2: QB output frequency equal to CLKx frequency times the multiplier ; QA output frequency equal to CLKx. NOTE 3: Maximum frequency of 240MHz valid for VCC = 3.3V ± 5% only.
8752CY
www.icst.com/products/hiperclocks.html
4
REV. A AUGUST 19, 2002
Integrated Circuit Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 47.9°C/W (0 lfpm) -65°C to 150°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx Inputs, VI O u t p u t s , VO Package Thermal Impedance, JA Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Positive Supply Voltage Analog Supply Voltage Output Supply Voltage Positive Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 105 15 20 Units V V V mA mA mA
TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage CLK0, CLK1, FB_IN, CLK_SEL, DIV_SELA1, DIV_SELA0, DIV_SELB1, DIV_SELB0, MR/nOE PLL_SEL CLK0, CLK1, FB_IN, CLK_SEL, DIV_SELA1, DIV_SELA0, DIV_SELB1, DIV_SELB0, MR/nOE PLL_SEL VOH Output High Voltage; NOTE 1 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 Units V V
IIH
Input High Current
VDD = VIN = 3.465V
150
µA
VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V
5
µA
-5
µA
IIL
Input Low Current
-150 2.4 0.5
µA V V
VOL Output Low Voltage; NOTE 1 NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information Section, "3.3V Output Load Test Circuit".
8752CY
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5
REV. A AUGUST 19, 2002
Others parts begin by 87
87-1 87-2
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