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Details, datasheet, quote on part number:ICS507M-02IT
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Datasheet text preview:
ICS507-01/02 PECL Clock Synthesizer
Description
The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz (or other high speed) differential PECL clock output from a low frequency crystal input. Using Phase-Locked-Loop (PLL) techniques, the devices use a standard fundamental mode crystal to produce output clocks up to 200 MHz. Stored in each chip's ROM is the ability to generate a selection of different multiples of the input reference frequency, including an exact 155.52 MHz clock from common crystals. For lowest jitter and phase noise on a 155.52 MHz clock, a 19.44 MHz crystal and the x8 selection can be used. This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. For applications which require defined input to output timing, use the ICS527-02.
Features
· Packaged as 16 pin narrow SOIC · Input crystal frequency of 5 - 27 MHz · Input clock frequency of 5 - 52 MHz · Enable usage of common low-cost crystal · Differential PECL output clock frequencies up to 200 MHz · Duty cycle of 49/51 · Operation voltage of 3.3 V or 5.0 V (±5%) · Ideal for SONET applications and oscillator manufacturers · Advanced, low power CMOS process · Industrial temperature versions available · Available in die form
Block Diagram
GND
VDD
1.1k RES
S0:1
2 Clock Synthesis and Control Circuitry
Output Buffer
270 62
PECL
Crystal or clock
VDD 62 PECL 270
X1
X2
Clock Buffer/ Crystal Oscillator
Output Buffer
Output Enable (both outputs) Output resistor values shown are for unterminated lines. Refer to MAN09 for additional information.
1 Revision 022002 Integrated Circuit Systems, Inc. · 525 Race Street · San Jose ·CA ·95126· (408)295-9800tel · www.icst.com
MDS 507 G
ICS507-01/02 PECL Clock Synthesizer
Pin Assignment Clock Multiplier Select Table
S1 0 0 0 M M M 1 1 1 S0 0 M 1 0 M 1 0 M 1 Multiplier 9.72X* 10X 12X 6.25X 8X 5X 2X 3X 4X *For ICS 507-01 or ICS507-02 at 3.3V, use this selection to get 155.52 MHz from a 16 MHz input. ICS507-02 at 5V requires a minimum input of 17.5 MHz on this setting. For lowest phase noise generation of 155.52 MHz, use a 19.44 MHz crystal and the 8X selection.
X1/ICLK VDD VDD S1 GND GND NC PECL
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
X2 NC S0 OE NC NC RES PECL
16 pin narrow (150 mil) SOIC
0 = connect pin directly to ground 1 = connect pin directly to VDD M = leave unconnected (floating)
Pin Descriptions
Number Name Type D e s c r i p t i o n 1 X1/ICLK XI Crystal or clock connection. Connect to a fundamental parallel mode crystal, or clock. 2 VDD P VDD. Connect to +3.3 V or +5 V, and to VDD on pin 3. 3 VDD P VDD. Connect to VDD on pin 2. Decouple with pin 5. 4 S1 TI Multiplier select pin 1. Determines output frequency per table above. 5 GND P Connect to ground. 6 GND P Connect to ground. 7 NC No connect. No internal connection. 8 PECL O PECL Output. Connect to resistor load as shown on page one. 9 PECL O Complementary PECL Output. Connect to resistor load as shown on page one. 10 RES I Bias Resistor Input. Connect a resistor between this pin and VDD. 11 NC No connect. No internal connection. 12 NC No connect. No internal connection. 13 OE I Output Enable. Tri-states both outputs when low. Internal pull-up. 14 S0 TI Multiplier select pin 0. Determines output frequency per table above. 15 NC No connect. No internal connection. 16 X2 XO Crystal connection. Connect to crystal, or leave unconnected for clock input. Key: I=Input, O=output, TI=tri-level input, P=power supply connection; XI, XO=crystal connections
2 Revision 022002 Integrated Circuit Systems, Inc. · 525 Race Street · San Jose ·CA ·95126· (408)295-9800tel · www.icst.com
MDS 507 G
ICS507-01/02 PECL Clock Synthesizer
Electrical Specifications
Parameter Conditions Minimum Typical Maximum Units ABSOLUTE A B S O L U T E MAXIMUM RATINGS (stresses beyond these can permanently damage the device) Supply Voltage, VDD Referenced to GND 7 V Inputs Referenced to GND -0.5 VDD+0.5 V Clock Output Referenced to GND -0.5 VDD+0.5 V Ambient Operating Temperature ICS507M-0x 0 70 °C ICS507M-0xI -40 85 °C Soldering Temperature Max of 20 seconds 260 °C Storage temperature -65 150 °C D C CHARACTERISTICS (VDD = 5.0 V unless otherwise noted) Operating Voltage, VDD 3.0 5.5 V Input High Voltage, VIH ICLK only VDD/2 + 1 VDD/2 V Input Low Voltage, VIL ICLK only VDD/2 VDD/2-1 V Input High Voltage, VIH S0, S1 VDD-0.5 V Input Low Voltage, VIL S0, S1 0.5 V Output High Voltage, VOH Note 2 VDD-1.2 V Output Low Voltage, VOL Note 2 VDD-2.0 V IDD Operating Supply Current, note 3 No Load, 155.52MHz 63 mA Internal Crystal Capacitance, X1 and X2 Pins 1, 8 26 pF Input Capacitance S0, S1 5 pF A C CHARACTERISTICS (VDD = 3.3, 5.0 V unless otherwise noted) Input Crystal Frequency 5 27 MHz Input Clock Frequency 5 52 MHz Output Frequency, ICS507-01 0 to 70°C VDD = 5.0 V 10 200 MHz 0 to 70°C VDD = 3.3 V 10 156 MHz Output Frequency, ICS507-01I -40 to 85°C VDD = 3.3 V or 5.0 V 10 125 MHz Output Frequency, ICS507-02I 0 to 70°C VDD = 5.0 V 125 200 MHz Note 5 0 to 70°C VDD = 3.3 V 125 200 MHz -40 to 85°C VDD = 3.3 V or 5.0 V 125 185 MHz Output Clock Duty Cycle 48 52 % PLL Bandwidth 10 kHz Absolute Clock Period Jitter Deviation from mean ±75 ps One Sigma Clock Period Jitter 20 ps Notes: 1) All typical values are at 5.0 V and 25°C unless otherwise noted. 2) VOH and VOL can be set by the external resistor values on the PECL outputs. 3) IDD includes the current through the external resistors, which can be modified. 4) The phase relationship between input and output can change at power up. For a fixed phase relationship, see one of the ICS zero delay buffers. 5) Except S1=0, S0=0 setting (This setting specific to 16 MHz in, 155.52 MHz out).
3 Revision 022002 Integrated Circuit Systems, Inc. · 525 Race Street · San Jose ·CA ·95126· (408)295-9800tel · www.icst.com
MDS 507 G
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