|
Details, datasheet, quote on part number:ICS511M
| |
Datasheet text preview:
ICS511
LOCOTM PLL CLOCK MULTIPLIER
Description
The ICS511 LOCOTM is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands for Low Cost Oscillator, as it is designed to replace crystal oscillators in most electronic systems. Using Phase-Locked-Loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal to produce output clocks up to 200 MHz. Stored in the chip's ROM is the ability to generate nine different multiplication factors, allowing one chip to output many common frequencies (see table on page 2). The device also has an output enable pin which tri-states the clock output when the OE pin is taken low. This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. For applications which require defined input to output skew, use the ICS570B.
Features
· Packaged as 8 pin SOIC or die · Upgrade of popular ICS501 with:
- changed multiplier table - faster operating frequencies - output duty cycle at VDD/2 Zero ppm multiplication error Input crystal frequency of 5 - 27 MHz Input clock frequency of 2 - 50 MHz Output clock frequencies up to 200 MHz Extremely low jitter of 25 ps (one sigma) Compatible with all popular CPUs Duty cycle of 45/55 up to 200 MHz Mask option for nine selectable frequencies Operating voltage of 3.3V or 5V Tri-state output for board level testing Industrial temperature version available Advanced, low power CMOS process
· · · · · · · · · · · ·
Block Diagram
VDD
S 1 :0 X 1 /IC L K C r y s t a l or C lo c k input X2
2
C ry s ta l O s c il l a t o r
P L L Clock M u l t ip l ie r C irc u it ry a n d ROM
CLK
O p t io n a l crystal capacitors GND
OE
MDS 511 E Integrated Circuit Systems
q
1
525 R a c e St r e e t , S a n Jose, CA 95126
q
Revision 101102 te l (40 8 ) 29 5 - 9 8 0 0
q
w w w. i c s t . c o m
ICS511 LOCOTM PLL Clock Multiplier
Pin Assignment
Clock Output Table
S1 0 S0 0 M 1 0 M 1 0 M 1 CLK 4X input 5.333X input 5X input 2.5X input 2X input 3.333X input 6X input 3X input 8X input
X1 / I CL K VDD GN D S1
1 2 3 4
8 7 6 5
X2 OE S0 CL K
0 0 M M M 1 1 1
8 Pi n ( 1 5 0 mi l ) SOI C
0 = connect directly to ground 1 = connect directly to VDD M = leave unconnected (floating)
Common Output Frequency Examples (MHz)
Output Input Selection (S1, S0) Output Input Selection (S1, S0) 20 10 M, M 66.66 20 M, 1 24 12 M, M 72 12 1, 0 30 10 1, M 75 25 1, M 32 16 M, M 80 10 1, 1 33.33 16.66 M, M 83.33 25 M, 1 37.5 15 M, 0 90 15 1, 0 40 10 0, 0 100 20 0, 1 48 12 0, 0 120 15 1, 1 50 20 M, 0 125 25 0, 1 60 10 1, 0 133.3 25 0, M 64 16 0, 0 150 25 1, 0
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8
Pin Nam e
XI/ICLK VDD GND S1 CLK S0 OE X2
Pin Type
Input Power Power Tri-level Iinput Output Tri-level Input Input Output
Pin Description
Crystal connection or clock input. Connect to +3.3V or +5V. Connect to ground. Select 1 for output clock. Connect to GND or VDD or float. Clock output per table above. Select 0 for output clock. Connect to GND or VDD or float. Output enable. Tri-states CLK output when low. Internal pull-up. Crystal connection. Leave unconnected for clock input.
MDS 511 E I n t e g r a t e d C i r c u i t Syst e m s
q
2
52 5 Race Str e e t , San Jose, C A 9 5 1 2 6
q
Revision 101102 tel ( 4 0 8 ) 295- 9 8 0 0
q
w w w. i c s t . c o m
ICS511 LOCOTM PLL Clock Multiplier
External Components
Decoupling Capacitor
As with any high performance mixed-signal IC, the ICS511 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01µF must be connected between VDD and the GND. It must be connected close to the ICS501 to minimize lead inductance. No external power supply filtering is required for the ICS501.
used. The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors, if needed, must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (CL -12pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 8 pF [(16-12) x 2] = 8.
Series Termination Resistor
A 33 terminating resistor can be used next to the CLK pin for trace lengths over one inch.
Crystal Load Capacitors
The total on-chip capacitance is approximately 12 pF. A parallel resonant, fundamental mode crystal should be
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS511. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Soldering Temperature 7V
Rating
-0.5V to VDD+0.5V -40 to +85°C -65 to +150°C 260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
0 +3.0
Typ.
Max.
+70 +5.5
Units
°C V
MDS 511 E I n t e g r a t e d C i r c u i t Syst e m s
q
3
52 5 Race Str e e t , San Jose, C A 9 5 1 2 6
q
Revision 101102 tel ( 4 0 8 ) 295- 9 8 0 0
q
w w w. i c s t . c o m
|
|
