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Details, datasheet, quote on part number:ICS512MI
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Datasheet text preview:
ICS512 LOCOTM PLL Clock Multiplier
Description
The ICS512 LOCOTM is the most cost effective way to generate a high quality, high frequency clock output and a reference clock from a lower frequency crystal or clock input. The name LOCO stands for LOw Cost Oscillator, as it is designed to replace crystal oscillators in most electronic systems. Using Phase-Locked-Loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal to produce output clocks up to 200 MHz. With a reference output, this chip plus an inexpensive crystal can replace two oscillators. Stored in the chip's ROM is the ability to generate nine different popular multiplication factors, allowing one chip to output many common frequencies (see page 2). This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. For applications which require defined input to output timing, use the ICS570B.
Features
· Packaged as 8 pin SOIC or die · Upgrade of popular ICS502 with: - changed multiplier table - higher operating frequencies · Zero ppm multiplication error · Easy to cascade with other 5xx series · Input crystal frequency of 5 - 27 MHz · Input clock frequency of 2 - 50 MHz · Output clock frequencies up to 200 MHz · Compatible with all popular CPUs · Duty cycle of 45/55 up to 200 MHz · Mask option for 9 selectable frequencies · Operating voltages of 3.0 to 5.5V · Industrial temperature version available · Advanced, low power CMOS process
Block Diagram
VDD GND
S1, S0
2 PLL Clock Synthesis and Control Circuitry
Output Buffer
CLK
Crystal or clock input X1/ICLK Crystal Oscillator X2
Output Buffer
REF
Optional crystal capacitors
MDS 512 D
1
Revision 021402
Integrated Circuit Systems, Inc. · 525 Race Street · San Jose ·CA·95126·(408) 295-9800tel · www.icst.com
ICS512 LOCOTM PLL Clock Multiplier
Pin Assignment
X1/ICLK VDD GND REF 1 2 3 4 8 7 6 5 X2 S1 S0 CLK
Clock Output Table
S1 0 0 0 M M M 1 1 1 S0 0 M 1 0 M 1 0 M 1 CLK 4X input 5.333X input 5X input 2.5X input 2X input 3.333X input 6X input 3X input 8X input
0 = connect directly to ground. 1 = connect directly to VDD. M = leave unconnected (floating).
Common Output Frequencies Examples (MHz)
Output Input Selection (S1, S0) Output
20 10 M, M
24 12 M, M 72 12 1, 0
30 10 1, M 75 25 1, M
32 16 M, M 80 10 1, 1
33.33 16.66 M, M 83.33 25 M, 1
37.5 15 M, 0 90 15 1, 0
40 10 0, 0 100 20 0, 1
48 12 0, 0 120 15 1, 1
50 20 M, 0 125 25 0, 1
60 10 1, 0 133.3 25 0, M
64 16 0, 0 150 25 1, 0
66.66 Input 20 Selection (S1, S0) M, 1
Note that all of the above outputs are achieved by using a common, inexpensive 10MHz to 25MHz crystal. Consult ICS on how to achieve other output frequencies.
Pin Descriptions
Number
1 2 3 4 5 6 7 8
Name X1/ICLK VDD GND REF CLK S0 S1 X2
Type XI P P O O TI TI XO
Description Crystal connection or clock input. Connect to +3.3V or +5V. Connect to ground. Buffered crystal oscillator output clock. Clock output per Table above. Multiplier select pin 0. Connect to GND or VDD or float (no connection). Multiplier select pin 1. Connect to GND or VDD or float (no connection). Crystal connection. Leave unconnected for clock input.
Key: XI/XO = crystal connections, TI = tri-level input, O = output, P = power supply connection
MDS 512 D
2
Revision 021402
Integrated Circuit Systems, Inc. · 525 Race Street · San Jose ·CA·95126·(408) 295-9800tel · www.icst.com
ICS512 LOCOTM PLL Clock Multiplier
Electrical Specifications
Parameter Conditions Minimum Typical Maximum Units ABSOLUTE A B S O L U T E MAXIMUM RATINGS (stresses beyond these can permanently damage the device) Supply Voltage, VDD Referenced to GND 7 V Inputs Referenced to GND -0.5 VDD+0.5 V Clock Output Referenced to GND -0.5 VDD+0.5 V Ambient Operating Temperature 0 70 °C ICS512MI only -40 85 °C Soldering Temperature Max of 10 seconds 260 °C Storage temperature -65 150 °C D C CHARACTERISTICS (VDD = 3.3V unless otherwise noted) Operating Voltage, VDD 3 5.5 V Input High Voltage, VIH, ICLK only ICLK (Pin 1) (VDD/2)+1 VDD/2 V Input Low Voltage, VIL, ICLK only ICLK (Pin 1) VDD/2 (VDD/2)-1 V Input High Voltage, VIH S0, S1 VDD-0.5 V Input Low Voltage, VIL S0, S1 0.5 V Output High Voltage, VOH, CMOS high IOH=-8mA VDD-0.4 V Output High Voltage, VOH IOH=-12mA 2.4 V Output Low Voltage, VOL IOL=12mA 0.4 V IDD Operating Supply Current, 20 MHz crystal No Load, 100MHz 9 mA Short Circuit Current CLK output ±70 mA Input Capacitance, S1, S0 Pins 6, 7 4 pF A C CHARACTERISTICS (VDD = 3.3V unless otherwise noted) Input Frequency, crystal input 5 27 MHz Input Frequency, clock input 2 50 MHz Output Frequency, VDD = 4.5 to 5.5V 0 to +70 °C 14 200 MHz Note 1 -40 to +85 °C 14 160 MHz Output Frequency, VDD = 3.0 to 3.6V 0 to +70 °C 14 160 MHz Note 1 -40 to +85 °C 14 145 MHz Output Clock Rise Time 0.8 to 2.0V 1 ns Output Clock Fall Time 2.0 to 0.8V 1 ns Output Clock Duty Cycle at VDD/2 45 49 to 51 55 % Absolute Clock Period Jitter Deviation from mean ±200 ps One Sigma Clock Period Jitter 80 ps Note 1: The phase relationship between input and output clocks can change at power up. For a fixed phase relationship, see the ICS570 or the ICS527.
MDS 512 D
3
Revision 021402
Integrated Circuit Systems, Inc. · 525 Race Street · San Jose ·CA·95126·(408) 295-9800tel · www.icst.com
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