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Details, datasheet, quote on part number:ICS513M
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Datasheet text preview:
ICS513 L O C O TM PLL Clock Generator
Description
The ICS513 LOCOTM is the most cost effective way to generate a high quality, high frequency clock output from a 14.31818 MHz crystal or clock input. The name LOCO stands for LOw Cost Oscillator, as it is designed to replace crystal oscillators in many electronic systems. Using Phase-Locked-Loop (PLL) techniques, the device uses a standard, inexpensive crystal to produce output clocks up to 100 MHz. Stored in the chip's ROM is the ability to generate 5 different output frequencies, allowing one chip to work in different speed processor systems. The device also has a power down mode that turns off the clock outputs when both select pins are low. In this mode, the internal PLL is not running.
Features
· Packaged as 8 pin SOIC · ICS' lowest cost PLL clock plus reference · Produces common computer frequencies · Input crystal frequency typically 14.3182 MHz · Output clock frequencies up to 100 MHz · Low jitter - 40 ps one sigma · Compatible with all popular CPUs · Duty cycle of 45/55 · Custom frequencies available · Operating voltages of 3.0 to 5.5 V · Power down mode turns off chip · 25mA drive capability at TTL levels · Advanced, low power CMOS process
Block Diagram
V D D GND 2 S1, S0 PLL Clock Synthesis and Control Circuitry Output Buffer CLK
14.31818 MHz crystal or clock X1/ICLK
Crystal Oscillator
X2
Output Buffer
REF
Optional crystal capacitors
1 Revision 080699 Printed 12/4/00 Integrated Circuit Systems · 525 Race Street · San Jose · CA· 95126 · (408)295-9800tel· (408)295-9818fax
MDS 513 B
ICS513 L O C O TM PLL Clock Generator
Pin Assignment
X1/ICLK VDD GND REF 1 2 3 4 8 7 6 5 X2 S1 S0 CLK
Clock Decoding Table (MHz) with 14.31818MHz Crystal or Clock Input
S1 0 0 M M 1 1 S0 0 1 0 1 0 1 CLK Multiplier Power Down CLK 100 6.984 24 1.676 14.31818 1 48 3.353 3.6864 0.2576 Accuracy 1 ppm 1 ppm 0 ppm 0.017% 0.044%
0 = connect directly to ground. 1 = connect directly to VDD. M = leave unconnected (floating). CLK and REF stop low in power down state.
Pin Descriptions
Number 1 2 3 4 5 6 7 8 Name X1/ICLK VDD GND REF CLK S0 S1 X2 Type I P P O O TI TI O Description Crystal connection to 14.31818 MHz crystal or clock input. Connect to +3.3 V or +5 V. Connect to ground. Reference 14.31818 MHz crystal oscillator buffered clock output. Clock output per table above. Select 0 for output clock. Connect to GND or VDD or float. See table above. Select 1 for output clock. Connect to GND or VDD or float. See table above. Crystal connection to 14.31818 MHz crystal. Leave unconnected for clock input.
Key: I = Input, TI = Tri-Level Input, O = output, P = power supply connection
Notes: 1. With S1 = S0 = 0, the internal PLL is turned off and the CLK output stops low. The crystal oscillator and REF output are still active. 2. With a clock input, the phase relationship between the input and output clocks can change each time the device is powered on. If a fixed phase relationship is required, please use our ICS571 or other zero delay multiplier.
2 Revision 080699 Printed 12/4/00 Integrated Circuit Systems · 525 Race Street · San Jose · CA· 95126 · (408)295-9800tel· (408)295-9818fax
MDS 513 B
ICS513 L O C O TM PLL Clock Generator
Electrical Specifications
Parameter Conditions Minimum Typical ABSOLUTE ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device) Supply Voltage, VDD Referenced to GND Inputs Referenced to GND -0.5 Clock Output Referenced to GND -0.5 Ambient Operating Temperature 0 Soldering Temperature Max of 10 seconds Storage temperature -65 DC CHARACTERISTICS (VDD = 5.0 V unless otherwise noted) Operating Voltage, VDD 3 Input High Voltage, VIH, ICLK only ICLK (Pin 1) (VDD/2)+1 VDD/2 Input Low Voltage, VIL, ICLK only ICLK (Pin 1) VDD/2 Input High Voltage, VIH S0 2 Input Low Voltage, VIL S0 Input High Voltage, VIH S1 VDD-0.5 Input Low Voltage, VIM S1 VDD/2 Input Low Voltage, VIL S1 Output High Voltage, VOH IOH=-25mA 2.4 Output Low Voltage, VOL IOL=25mA IDD Operating Supply Current No Load, 100 MHz 20 IDD Power Down Supply Current, 3.3 V S1 = S0 = 0 1.5 Short Circuit Current CLK output ±70 On-Chip Pull-up Resistor Pin 6 270 Input Capacitance, S1, S0 Pins 6, 7 4 AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted) Input Frequency, crystal input 5 14.31818 Input Frequency, clock input 2 14.31818 Output Frequency VDD = 4.5 to 5.5 V 14 100 Output Frequency VDD = 3.0 to 3.6 V 14 100 Output Clock Rise Time 0.8 to 2.0V 1 Output Clock Fall Time 2.0 to 0.8V 1 Output Clock Duty Cycle 1.5V, up to 140 MHz 45 49 to 51 Power up time, from PD to outputs stable 5 Power down time, from running to PD state Absolute Clock Period Jitter Deviation from mean ±110 One Sigma Clock Period Jitter 40 Maximum 7 VDD+0.5 VDD+0.5 70 260 150 5.5 (VDD/2)-1 0.8 Units V V V °C °C °C V V V V V V V V V V mA mA mA k pF MHz MHz MHz MHz ns ns % ms ns ps ps
0.5 0.4
27 50 140 100
55 10 50
3 Revision 080699 Printed 12/4/00 Integrated Circuit Systems · 525 Race Street · San Jose · CA· 95126 · (408)295-9800tel· (408)295-9818fax
MDS 513 B
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