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Details, datasheet, quote on part number:ICS650-05
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Datasheet text preview:
ICS650-05 HDTV Clock Synthesizer
Description
The ICS650-05 is a low cost, low jitter, high performance clock synthesizer designed to produce 74.175824 MHz and 74.250000 MHz as necessary for HDTV applications. Using our patented analog PhaseLocked Loop (PLL) techniques, the device uses a 27.0 MHz clock or fundamental crystal input to produce buffered, fixed clocks and a selectable frame rate clock for HDTV systems.
Features
· Packaged in 20 pin tiny SSOP (QSOP) · Input Frequency of 27.0 MHz · Zero ppm synthesis error in output clocks · Provides fixed 13.5 MHz, dual 27.0 MHz, and 54.0 MHz output clocks with a selectable Frame Rate Clock of 74.175824 MHz or 74.250000 MHz · Ideal for HDTV applications · 3.3 V or 5.0 V operating voltage.
Block Diagram
VDD 5
Output Buffer FRS Clock Synthesis and Control Circuit Output Buffer Output Buffer
FRCLK
54.0 MHz
13.5 MHz
Crystal or Clock Input
X1/ICLK Input Buffer/Crystal Oscillator X2
Output Buffer Output Buffer
27.0 MHz
27 MHz
27.0 MHz
5 OE (all outputs) GND
MDS 650-05 B
1
Revision 100301
Integrated Circuit Systems · 525 Race Street · San Jose · CA · 95126 · (408) 295-9800tel · www.icst.com
ICS650-05 HDTV Clock Synthesizer
Pin Assignment
VDD X2 X1/ICLK VDD VDD GND NC 27M 13.5M GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD OE FRS FRCLK VDD GND GND 54M 27M GND F R C L K Output Select Table (in MHz)
F R S Pin 18 F R C L K Pin 17
0 1
74.175824 74.250000
20 pin SSOP (QSOP)
Pin Descriptions
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Name
VDD X2 X1/ICLK VDD VDD GND NC 27M 13.5M GND GND 27M 54M GND GND VDD FRCLK FRS OE VDD
Type D e s c r i p t i o n
P XO XI P P P O O P P O O P P P O I I P Connect to +3.3 V or +5.0 V. Must be same as other VDDs. Crystal connection to a 27.0 MHz crystal or leave unconnected for clock input Crystal connection. Connect to a 27.0 MHz fundamental mode crystal or clock input. Connect to +3.3 V or +5.0 V. Must be same as other VDDs. Connect to +3.3 V or +5.0 V. Must be same as other VDDs. Connect to ground. No Connect. Do not connect anything to this pin. 27 MHz buffered reference output. 13.5 MHz clock output. Connect to ground. Connect to ground. 27 MHz buffered clock output. 54 MHz buffered clock output. Connect to ground. Connect to ground. Connect to +3.3 V or +5.0 V. Must be same as other VDDs. Frame Rate Clock as shown on table. Frame Rate Frequency Select input pin. Determines FRCLK output as shown on table. Output Enable. Tri-states all clocks when low. Connect to +3.3 V or +5.0 V. Must be same as other VDDs.
Key: I = Input with internal pull-up; O = output; P = power supply connection; XI, XO = crystal connections
MDS 650-05 B
2
Revision 100301
Integrated Circuit Systems · 525 Race Street · San Jose · CA · 95126 · (408) 295-9800tel · www.icst.com
ICS650-05 HDTV Clock Synthesizer
Electrical Specifications
Parameter Conditions Minimum Typical Maximum Units
ABSOLUTE A B S O L U T E MAXIMUM RATINGS (note 1) Supply voltage, VDD Referenced to GND Inputs and Clock Outputs Referenced to GND -0.5 Ambient Operating Temperature 0 Soldering Temperature Max of 10 seconds Storage temperature -65 D C CHARACTERISTICS (VDD = 3.3V or 5V unless noted) Operating Voltage, VDD 3.0 Input High Voltage, VIH X1/ICLK VDD/2+1 Input Low Voltage, VIL XI/ICLK Input High Voltage, VIH FRS, OE 2 Input Low Voltage, VIL FRS, OE Output High Voltage, VOH VDD=3.3V, IOH=-8mA 2.4 Output Low Voltage, VOL VDD=3.3V, IOL=8mA Output High Voltage, VOH, VDD = 3.3 or 5V IOH=-8mA VDD-0.4 Operating Supply Current, IDD, at 5V No Load Operating Supply Current, IDD, at 3.3V No Load Short Circuit Current, VDD = 3.3 V Each output Input Capacitance Except X1 A C CHARACTERISTICS (VDD = 3.3V or 5V unless noted) Input Crystal or Clock Frequency Output Clocks Accuracy (synthesis error) All clocks Output Clock Rise Time 0.8 to 2.0V Output Clock Fall Time 2.0 to 0.8V Output Clock Duty Cycle At VDD/2 40 VDD = 3.3V, 13.5M, FRCLK, 27M (pin 12) One Sigma Jitter VDD=3.3V, 27M (pin8), 54M VDD=5.0V, except 27M (pin8) VDD = 5.0V, 27M (pin 8) VDD=3.3V, except 27M (pin 8), 54M VDD=3.3V, 27M (pin 8), 54M VDD=5.0V
7 VDD+0.5 70 260 150 5.5 VDD/2-1 0.8 0.4 26 14 ±50 5 27 1 1.5 1.5 60
V V °C °C °C V V V V V V V V mA mA mA pF MHz ppm ns ns % ps ps ps ps ps ps ps
50 50 125 50 65 ±125 ±350 ±175
Absolute Clock Period Jitter
N o t e s : 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
E x t e r n a l Components A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 µF should be connected between VDD and GND on pins 4 and 6, and 16 and 14, and a 33 terminating resistor may be used on each clock output if the trace is longer than 1 inch.
MDS 650-05 B
3
Revision 100301
Integrated Circuit Systems · 525 Race Street · San Jose · CA · 95126 · (408) 295-9800tel · www.icst.com
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