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Details, datasheet, quote on part number:ICS650-12
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Datasheet text preview:
ICS650-12 MPEG Clock Synthesizer
Description
The ICS650-12 is a low cost, low jitter, high performance clock synthesizer designed to produce fixed clock outputs of 13.5 MHz and 27.0 MHz and four selectable clock outputs of two Processor Clocks (PCLK1 and PCLK2), Audio Clock (ACLK), and Communications Clock (CCLK). Using our patented analog PhaseLocked Loop (PLL) techniques, the device uses a 27.0 MHz clock or fundamental crystal input to produce clocks ideal for Digital Video/MPEGbased applications.
Features
· · · · Packaged in 20 pin tiny SSOP (QSOP) Input Frequency of 27.0 MHz Zero ppm synthesis error in output clocks Provides fixed 13.5 MHz and 27.0 MHz. Also provides two selectable Processor Clocks, one Audio Clock, and one Communications Clock · Ideal for Digital Video/MPEG-based applications · 3.3 V or 5.0 V operating voltage · Entire chip powers down (when CS1=CS0=0)
Block Diagram
Output Buffer PS2:0 Clock Synthesis and Control Circuitry Output Buffer Output Buffer Output Buffer Output Buffer ÷2 27.0 MHz crystal or clock Input Buffer/Crystal Oscillator Output Buffer
PCLK1 PCLK2 ACLK CCLK
AS2:0 CS1:0
13.5 MHz
27.0 MHz
1 Revision 113000 Integrated Circuit Systems, Inc. · 525 Race Street · San Jose ·CA·95126· (408) 295-9800tel · www.icst.com
MDS 650-12 A
ICS650-12 MPEG Clock Synthesizer
Pin Assignment
PS2 X2 X1 VDD CS1 GND ACLK PCLK1 CS0 AS2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PS1 PS0 CCLK PCLK2 VDD AS1 GND 13.5M 27M AS0 PCLK1 and PCLK2 Select Table (in MHz) PS2 PS1 PS0 PCLK1 PCLK2 0 0 0 108.00 54.00 0 0 1 55.00 27.5 0 1 0 66.67 33.33 0 1 1 80.00 40.00 1 0 0 54.00 27.00 1 0 1 81.00 40.5 1 1 0 50.00 25.00 1 1 1 60.00 30.00 ACLK Select Table (in MHz) AS2 AS1 AS0 ACLK 0 0 0 12.288 0 0 1 11.2896 0 1 0 8.192 0 1 1 24.576 1 0 0 8.192 1 0 1 16.9344 1 1 0 18.432 1 1 1 11.2896 CCLK Select Table (in MHz) CS1 CS0 CCLK 0 0 All off* 0 1 20.00 1 0 66.6666 1 1 24.576 *Note: Entire chip powers down (outputs stop low) when CS1 = CS0 = 0.
20 pin SSOP (QSOP)
Pin Descriptions
Pin # 1 2 3 4, 16 5 6, 14 7 8 9 10 11 12 13 15 17 18 19 20 Name PS2 X2 X1 VDD CS1 GND ACLK PCLK1 CS0 AS2 AS0 27M 13.5M AS1 PCLK2 CCLK PS0 PS1 Type I XO XI P I P O O I I I O O I O O I I Description Processor Clock Select Pin 2. See above table. Crystal connection to a 27.0 MHz crystal or leave unconnected for clock input Crystal connection. Connect to a 27.0 MHz fundamental mode crystal or clock input. Connect to +3.3 V or +5.0 V. Communications Clock Select Pin 1. See above table. Connect to ground. Audio Clock Output. See above table. Processor Clock Output 1. See above table. Communications Clock Select 0. See above table. Audio Clock Select Pin 2. See above table. Audio Clock Select Pin 0. See above table. 27 MHz buffered clock output. 13.5 MHz clock output. Audio Clock Select Pin 1. See above table. Processor Clock Output 2. See above table. Communications Clock Output. See above table. Processor Clock Select Pin 0. See above table. Prcoessor Clock Select Pin 1. See above table.
Key: I = Input with internal pull-up; O = output; P = power supply connection; XI, XO = crystal connections 2 Revision 113000 Integrated Circuit Systems, Inc. · 525 Race Street · San Jose ·CA·95126· (408) 295-9800tel · www.icst.com
MDS 650-12 A
ICS650-12 MPEG Clock Synthesizer
Electrical Specifications
Parameter Supply voltage, VDD Inputs and Clock Outputs Ambient Operating Temperature Soldering Temperature Storage temperature Operating Voltage, VDD Input High Voltage, VIH Input Low Voltage, VIL Output High Voltage, VOH Output Low Voltage, VOL Output High Voltage, VOH, VDD = 3.3 or 5V Operating Supply Current, IDD, at 5V Operating Supply Current, IDD, at 3.3V Short Circuit Current, VDD = 3.3 V Input Capacitance Input Crystal or Clock Frequency Output Clocks Accuracy (synthesis error) Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle One Sigma Jitter, ACLK Absolute Clock Period Jitter Notes: Conditions Referenced to GND Referenced to GND Max of 10 seconds -65 3.0 2 VDD=3.3V, IOH=-8mA VDD=3.3V, IOL=8mA IOH=-8mA No Load No Load Each output Except X1 2.4 0.4 VDD-0.4 39 22 ±50 7 27 0 Minimum Typical Maximum 7 VDD+0.5 70 260 150 5.5 0.8 Units V V
°C °C °C
ABSOLUTE ABSOLUTE MAXIMUM RATINGS (note 1)
-0.5 0
DC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
V V V V V V mA mA mA pF MHz ppm ns ns % ps ps ps ps
AC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
All clocks 0.8 to 2.0V 2.0 to 0.8V At VDD/2 VDD=3.3 V VDD=5.0 V
VDD=3.3 V, Except CCLK=20 MHz VDD=5.0 V, Except CCLK=20 MHz
40
50 100 40 ±300 ±200
1 1.5 1.5 60
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 µF should be connected between VDD and GND on pins 4 and 6, and 16 and 14, and a 33 terminating resistor may be used on each clock output if the trace is longer than 1 inch.
3 Revision 113000 Integrated Circuit Systems, Inc. · 525 Race Street · San Jose ·CA·95126· (408) 295-9800tel · www.icst.com
MDS 650-12 A
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