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Details, datasheet, quote on part number:ICS650-27
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Datasheet text preview:
ICS650-27
Networking Clock Source
Description
The ICS650-27 is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking chips, PCI devices, SDRAM, and ASICs. The ICS650-27 outputs all have zero ppm synthesis error. The ICS650-27 is pin compatible and functionally equivalent to the ICS650-07. It is a performance upgrade and is recommended for all new 3.3V designs. See the MK74CB214, ICS551, and ICS552-01 for non-PLL buffer devices which produce multiple low-skew copies of these output clocks. See the ICS570, ICS9112-16/17/18 for zero delay buffers that can synchronize outputs and other needed clocks.
Features
· Packaged in 20-pin (150 mil) SSOP (QSOP) · 12.5 MHz or 25 MHz fundamental crystal or clock · · · · · · · · ·
input Six output clocks with selectable frequencies SDRAM frequencies of 67, 83, 100, and 133 MHz Buffered crystal reference output Zero ppm synthesis error in all clocks Ideal for PMC-Sierra's ATM switch chips Full CMOS output swing with 25 mA output drive capability at TTL levels Advanced, low-power, sub-micron CMOS process Operating voltage of 3.3 V Industrial temperature only
Block Diagram
VDD 2
CL K A 1
ACS1:0 BCS1:0 CCS 2 2 C lo ck S yn th e sis and Control C ir c u it r y
/2
CL K A 2 CL K B 1
/2
CLK B2 CLKC1 CLKC2
X1/ICLK 25 or 12.5 MHz cyrstal or clock X2
C l oc k Bu ffe r/ C r ysta l O s c il la t o r 2
REFOUT
OE (all outputs)
GND
MDS 650-27 C I n t e g r a t e d Circuit Systems, Inc.
1
525 Race Street, San Jose, CA 95126
Revision 102303 tel (408) 297-1201
www.icst.com
ICS650-27 Networking Clock Source
Pin Assignment
ASC0 X2 X1/ICLK VDD ASC1 GND CLKC1 CLKC2 CLKB2 CLKB1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 BCS1 BCS0 REFOUT CLKA1 VDD OE GND CLKA2 DC CCS
20-pin (150 mil) SSOP
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Name
ACS0 X2 X1/ICLK VDD ACS1 GND CLKC1 CLKC2 CLKB2 CLKB1 CCS DC CLKA2 GND OE VDD CLKA1 REFOUT BCS0 BCS1
Pin Type
Input Input Input Power Input Power Output Output Output Output Input Output Power Input Power Output Output Input Input
Pin Description
A clock select 0. Selects outputs on CLKA1 and CLKA2 per table on page 3. Crystal connection. Connect to a fundamental crystal or leave unconnected for a clock input. Crystal connection. Connect to a fundamental crystal or clock input. Connect to +3.3 V or 5 V. Must be the same as pin 16. A clock select 1. Selects outputs on CLKA1 and CLKA2 per table on page 3. Internal pull-up. Connect to ground. Output Clock C1. Depends on setting of CCS per table on page 3. Output Clock C2. Depends on setting of CCS per table on page 3. Same as CLKC1. Output Clock B2. Depends on setting of BCS1, 0 per table on page 3. Output Clock B1. Depends on setting of BCS1, 0 per table on page 3. Clock C select pin. Selects outputs on CLKC1 and CLKC2 per table on page 3. Don't connect. Do not connect anything to this pin. Output Clock A2. Depends on setting of ACS1, 0 per table on page 3. Connect to ground. Output enable. Tri-states all outputs when low. Internal pull-up. Connect to +3.3 V or 5 V. Must be the same as pin 4. Output Clock A1. Depends on setting of ACS1, 0 per table on page 3. Buffered reference clock output. Same frequency as crystal or clock input. B clock select 0. Selects outputs on CLKB1 and CLKB2 per table on page 3. B clock select 1. Selects outputs on CLKB1 and CLKB2 per table on page 3. Internal pull-up.
MDS 650-27 C I n t e g r a t e d Circuit Systems, Inc.
2
525 Race Street, San Jose, CA 95126
Revision 102303 tel (408) 297-1201
www.icst.com
ICS650-27 Networking Clock Source
For a 25 MHz fundamental crystal or clock input, the following four tables apply:
A Clocks Select Table (outputs in MHz) ASC 1 0 0 0 1 1 1 ASC0 0 M 1 0 M 1 CLKA 1 100 Test 75 33.3333 Test 66.6667 CL K A 2 off (low) Test off (low) 16.6667 Test 33.3333 B Clocks Select Table (outputs in MHz) BSC1 0 0 0 1 1 1 BSC0 0 M 1 0 M 1 CLKB1 Test 66.6667 100 83.3333 Test 133.3333 CLKB2 Test 33.3333 50 41.6667 Test 66.6667
C Clocks Select Table (outputs in MHz) C CS 0 M 1 C LK C1 125 Test 75 CLKC 2 125 Test 75
Reference Output Clock Frequency (in MHz) REFOUT 25
For a 12.5 MHz fundamental crystal or clock input, the following four tables apply:
A Clocks Select Table (outputs in MHz) ASC 1 0 0 0 1 1 1 ASC0 0 M 1 0 M 1 CLKA 1 50 Test 37.5 16.6667 Test 33.3333 CL K A 2 off (low) Test off (low) 8.3333 Test 16.6667 B Clocks Select Table (outputs in MHz) BSC1 0 0 0 1 1 1 BSC0 0 M 1 0 M 1 CLKB1 Test 33.3333 50 41.6667 Test 66.6667 CLKB2 Test 16.6667 25 20.8333 Test 33.3333
C Clocks Select Table (outputs in MHz) C CS 0 M 1 C LK C1 62.5 Test 37.5 CLKC 2 62.5 Test 37.5
Reference Output Clock Frequency (in MHz) REFOUT 12.5
0 = connect directly to GND M = leave unconnected (automatically self biases to VDD/2) 1 = connect directly to VDD
MDS 650-27 C I n t e g r a t e d Circuit Systems, Inc.
3
525 Race Street, San Jose, CA 95126
Revision 102303 tel (408) 297-1201
www.icst.com
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