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Details, datasheet, quote on part number:ICS650-36
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Datasheet text preview:
ICS650-36
Networking & PCI Clock Source
Description
The ICS650-36 is a low cost frequency generator designed to support networking and PCI applications. Using analog/digital Phase Locked-Loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal input of 25 MHz to produce four output clocks supporting LAN, PCI, and 100M SDRAM functions. The device also has a power down feature that tri-states the clock outputs and turns off the PLL when the PDTS pin is taken low.
Features
· · · · · · · ·
Packaged in 16-pin TSSOP Replaces multiple crystals and oscillators Input crystal or clock frequency of 25 MHz Fixed reference output frequency of 25 MHz Selectable output frequencies of 33.3, 33.333, 50, 66.666, 100, and 125 MHz Duty cycle of 40/60 Operating voltage of 3.3 V Advanced, low-power CMOS process
Block Diagram
VDD 3
S2:0
3
Select/ Control Circuit
PLL1
CLK1
PLL2
CLK2
PLL3 X1/ICLK 25 MHz crystal input X2 Crystal Oscillator/ Clock Buffer
CLK3
REF
External capacitors may be required.
3 GND PDTS
(all outputs and PLLs)
MDS 650-36 B Integrated Circuit Systems
1
5 2 5 Race Street, San Jose, CA 9 5 1 2 6
Revision 102903 tel (408 ) 2 9 7 - 1 2 0 1 www.icst.co m
ICS650-36 Networking & PCI Clock Source
Pin Assignment
X2 X1 GND CLK3 PDTS S2 CLK2 VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD GND REF S0 VDD CLK1 GND S1
CLK Output Selection Table
S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 REF OFF ON ON ON ON ON ON ON CLK1 33.30 33.333 33.333 66.666 33.333 33.333 33.333 33.30 CLK2 50 33.333 66.666 66.666 50 50 66.666 50 CLK3 125 125 125 125 125 100 100 125
16-pin (173 mil) TSSOP
Note: All frequencies are in MHz.
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13
Pin Name
X2 X1 G ND CL K 3
Pin Type
Output Input Power Output
Pin Description
Crystal connection. Connect to 25 MHz crystal input or float for clock. Crystal connection. Connect to 25 MHz crystal or clock input. Connect to ground. Selectable clock output. See table above for frequency. Weak internal pull-down when tri-state. Powers down entire chip and tri-states outputs when low. Internal pull-up resistor. Select pin. Selects clock output frequency from table above. Internal pull-up resistor. Selectable clock output. See table above for frequency. Weak internal pull-down when tri-state. Connect to +3.3 V. Select pin. Selects clock output frequency from table above. Internal pull-up resistor. Connect to ground. Selectable clock output. See table above for frequency. Weak internal pull-down when tri-state. Connect to +3.3 V. Select pin. Selects clock output frequency from table above. Internal pull-up resistor.
PDTS S2 CL K 2 VDD S1 GND CLK1 VDD S0
Input Input Output Power Input Power Output Power Input
MDS 650-36 B I n t e g r a t e d C i r c u i t Syste m s
2
525 R a c e Street, San Jose, CA 9 5 1 2 6
Revision 102903 tel (40 8 ) 29 7 - 1 2 0 1 w w w . i c s t . c o m
ICS650-36 Networking & PCI Clock Source
Pin Number
14 15 16
Pin Name
REF GND VDD
Pin Type
Output Power Power
Pin Description
Reference 25 MHz clock output. Weak internal pull-down when tri-state. Connect to ground. Connect to +3.3 V.
External Components
Decoupling Capacitor
As with any high performance mixed-signal IC, the ICS650-36 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01µF must be connected between each VDD and the PCB ground plane. The value (in pF) of these crystal caps should equal (CL -6 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2] = 20.
PCB Layout Recommendations
Observed the following guidelines for optimum device performance and lowest output phase noise: 1) The 0.01µF decoupling capacitors should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pins should be kept as short as possible, as should the PCB trace to the ground via. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI the 33 series termination resistor, if needed, should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS650-36. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
Series Termination Resistor
Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20.
Crystal Load Capacitors
The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground.
MDS 650-36 B I n t e g r a t e d C i r c u i t Syste m s
3
525 R a c e Street, San Jose, CA 9 5 1 2 6
Revision 102903 tel (40 8 ) 29 7 - 1 2 0 1 w w w . i c s t . c o m
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