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Details, datasheet, quote on part number:ICS8430DY-11
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS8430-11
700MHZ, LOW JITTER CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
· Dual differential 3.3V LVPECL outputs · Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK · Output frequency up to 700MHz · Crystal input frequency range: 14MHz to 27MHz · VCO range: 200MHz to 700MHz · Parallel or serial interface for programming counter and output dividers · RMS period jitter: 9.5ps (maximum) · Cycle-to-cycle jitter: 25ps (maximum) · 3.3V supply voltage · 0°C to 70°C ambient operating temperature · Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8430-11 is a general purpose, dual output ,&6 Crystal-to-3.3V Differential LVPECL High FreH iPerC lockSTM q u e n c y Synthesizer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8430-11 has a selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK. The VCO operates at a frequency range of 200MHz to 700MHz. With the output configured to divide the VCO frequency by 2, output frequency steps as small as 2MHz can be achieved using a 16MHz crystal or reference clock. Output frequencies up to 700MHz can be programmed using the serial or parallel interfaces to the configuration logic. The low jitter and frequency range of the ICS8430-11 make it an ideal clock generator for most clock tree applications.
BLOCK DIAGRAM
VCO_SEL
PIN ASSIGNMENT
VCO_SEL nP_LOAD XTAL2
M4
M3
M2
M1
M0
XTAL_SEL TEST_CLK XTAL1 OSC XTAL2 ÷ 16 0 1 M5 M6 M7 M8 N0 1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23 22 XTAL1 TEST_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR
ICS8430-11
21 20 19 18 17
PLL
PHASE DETECTOR VCO ÷M ÷2 S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N2 CONFIGURATION INTERFACE LOGIC 0 ÷N 1
N1 N2 VEE FOUT0 nFOUT0 FOUT1 nFOUT1
MR
9 10 11 12 13 14 15 16
TEST VCC FOUT1 nFOUT1 V CCO FOUT0 nFOUT0 VEE
TEST
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
8430EY-11
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1
REV. A JUNE 13, 2003
Integrated Circuit Systems, Inc. FUNCTIONAL DESCRIPTION
ICS8430-11
700MHZ, LOW JITTER CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fxtal x 2M fVCO = 16 The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 16MHz reference are defined as 100 M 350. The frequency out is defined as follows: fout = fVCO = fxtal x 2M N 16 N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGHto-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N outputdivider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows:
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8430-11 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A parallel-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a 16MHz crystal, this provides a 1MHz reference frequency. The VCO of the PLL operates over a range of 200MHz to 700MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS8430-11 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 through N2 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remainsloaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hard-wired to set the M divider and N output divider to a
T1 0 0 1 1
T0 0 1 0 1
TEST Output LOW S_Data, Shift Register Input Output of M divider CMOS Fout
SERIAL LOADING
S_CLOCK
S_DATA
t
T1
S
T0
H
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
nP_LOAD
t
S
PARALLEL LOADING
M0:M8, N0:N2
M, N
nP_LOAD
t
S
t
H
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
8430EY-11
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REV. A JUNE 13, 2003
Integrated Circuit Systems, Inc.
ICS8430-11
700MHZ, LOW JITTER CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Type Input Input Input Input Power Output Power Output Power Output Description
TABLE 1. PIN DESCRIPTIONS
Number 1, 2, 3, 28, 29, 30 31, 32 4 5, 6 7 8, 16 9 10 11, 12 13 14, 15 Name M5, M6, M7, M0, M1, M2, M3, M4 M8 N0, N1 N2 VEE TEST VCC FOUT1, nFOUT1 VCCO FOUT0, nFOUT0
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS / LVTTL interface levels. Pullup Pulldown Determines output divider value as defined in Table 3C Function Table. LVCMOS / LVTTL interface levels. Pullup Negative supply pins. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. Core power supply pin. Differential output for the synthesizer. 3.3V LVPECL interface levels. Output supply pin. Differential output for the synthesizer. 3.3V LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inver ted 17 MR Input Pulldown outputs nFOUTx to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register 18 S_CLOCK Input Pulldown on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge 19 S_DATA Input Pulldown of S_CLOCK. LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the dividers. 20 S_LOAD Input Pulldown LVCMOS / LVTTL interface levels. 21 VCCA Power Analog supply pin. Selects between cr ystal or test inputs as the PLL reference source. 22 XTAL_SEL Input Pullup Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels. 23 TEST_CLK Input Pulldown Test clock input. LVCMOS / LVTTL interface levels. 24, 25 XTAL1, XTAL2 Input Cr ystal oscillator inputs. Parallel load input. Determines when data present at M8:M0 is 26 nP_LOAD Input Pulldown loaded into the M divider, and when data present at N2:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. 27 VCO_SEL Input Pullup LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
8430EY-11
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REV. A JUNE 13, 2003
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