|
|
Part: ICS8431-11
Category:
Timing Circuits
-> Clock Distribution
-> CPU/Memory Specific
Description: 200mhz, Low Jitter, Lvpecl Frequency Synthesizer
Company: Integrated Circuit System
Datasheet: Download ICS8431-11 datasheet File size : 407 kB
Request For quote: Find where to buy ICS8431-11
Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS8431-01
200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
FEATURES
· Fully integrated PLL · Differential 3.3V LVPECL output · 200MHz output frequency · 48% to 52% duty cycle · Crystal oscillator interface · Spread Spectrum Clocking (SSC) fixed at 1/2% modulation for environments requiring ultra low EMI. Typical10dB EMI reduction can be achieved with spread spectrum modulation · LVTTL / LVCMOS control inputs · PLL bypass modes supporting in-circuit testing and on-chip functional block characterization · 28 lead SOIC · RMS cycle-to-cycle jitter of 2ps · Typical cycle-to-cycle jitter of 18ps · 0° to 85°C ambiant operating temperature
GENERAL DESCRIPTION
T h e ICS8431-01 is a general purpose clock frequency synthesizer for IA64/32 application and H iPer Cl ockSTM a member of the HiPerClockSTM family of High P e r f o r m a n c e Clock Solutions from ICS. The ICS8431-01 consists of one independent low bandwidth PLL timing channel. A 16.666MHz crystal is used as the input to the on-chip oscillator. The M is configured to produce a fixed output frequency of 200MHz.
,&6
P r o g r a m m a b l e features of the ICS8431-01 support four operational modes. The four modes are spread spectrum clocking (SSC), non-spread spectrum clock and two test modes which are controlled by the SSC_CTL[1:0] pins. Unlike other synthesizers, the ICS8431-01 can immediately change spread-spectrum operation without having to reset the device. In SSC mode, the output clock is modulated in order to achieve a reduction in EMI. In one of the PLL bypass test m o d e s , the PLL is disconnected as the source to the d i f f e r e n t i a l output allowing an external source to be c o n n n e c t e d to the TEST_I/O pin. This is useful for incircuit testing and allows the differential output to be driven at a lower frequency throughout the system clock tree. In the other PLL bypass mode, the oscillator divider is used as the source to both the M and the Fout divide by 2. This is useful for characterizing the oscillator and internal dividers.
BLOCK DIAGRAM
XTAL1 OSC XTAL2 ÷ 16
PIN ASSIGNMENT
nc nc nc nc nc nc nc nc nc SSC_CTL0 SSC_CTL1 VEE TEST_I/O VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nc VDDI XTAL2 XTAL1 nc nc VDDA VEE RESERVED nc VDDO FOUT nFOUT VEE
PLL
PHASE DETECTOR VCO ÷M ÷2
FOUT nFOUT
TEST_I/O SSC_CTL0 SSC_CTL1 SSC Control Logic
ICS8431-01
28-Lead SOIC M Package Top View
ICS8431CM-01
www.icst.com/products/hiperclocks.html
1
REV. A JUNE 5, 2001
Integrated Circuit Systems, Inc.
ICS8431-01
200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
Type Unused Input Power Input / Output Power Power Output Power Reserve Power Power Input Power Pullup Description Unused pins. SSC control pins. LVTTL/LVCMOS interface levels. Ground pin for core and test output. Programmed as defined in Table 3 Function Table.. Power supply pin for core and test output. Ground pin for output. These differential outputs are main output drivers for the synthesizer. They are compatible with terminated positive referenced LVPECL logic. Power supply pin for output. Reserve pin. Ground pin. PLL power supply pin. Crystal oscillator input. Input and core power supply pin. Connect to 3.3V.
TABLE 1. PIN DESCRIPTIONS
Number 1-9, 19, 23, 24, 28 10, 11 12 13 14, 27 15 16, 17 18 20 21 22 25, 26 27 Name nc SSC_CTL0, SSC_CTL1 GND TEST_ I/O VDD GND nFOUT, FOUT VDDO RESERVED VEE VDDA XTAL1, XTAL2 VDDI
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Pin Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
TABLE 3. SSC CONTROL INPUTS FUNCTION TABLE
Inputs SSC_CTL1 SSC_CTL0 0 0 1 1 0 1 0 1 TEST_I/O Source Internal PLL External PLL SSC Disabled Enabled Disabled Disabled Outputs FOUT, TEST_I/O nFOUT fXTAL ÷ 16 fXTAL ÷ 32 ÷M 200MHz Hi-Z Test Clk 200MHz Input Hi-Z Operational Modes PLL bypass; Oscillator, oscillator, M and N dividers test mode. NOTE 1 Default SSC; Modulation Factor = ½ Percent Diagnostic Mode; NOTE 1 (1MHz Test Clk 200MHz) No SSC Modulation
NOTE 1: Used for in house debug and characterization.
ICS8431CM-01
www.icst.com/products/hiperclocks.html
2
REV. A JUNE 5, 2001
Integrated Circuit Systems, Inc.
ICS8431-01
200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 0°C to 85°C -65°C to 150°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Inputs Outputs Ambient Operating Temperature Storage Temperature
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V±5%, TA = 0°C TO 85°C
Symbol VDD VDDO VDDA VDDI IEE Parameter Power Supply Voltage Output Power Supply Voltage Analog Power Supply Voltage Input Power Supply Voltage Test Conditions Minimum 3.135 3.135 3.135 3.135 Typical 3.3 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 3.465 140 Units V V V V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V±5%, TA = 0°C TO 85°C
Symbol VIH Parameter Input High Voltage SSC_CTL0, SSC_CTL1, TEST_I/O SSC_CTL0, SSC_CTL1, TEST_I/O SSC_CTL0, SSC_CTL1, TEST_IO SSC_CTL0, SSC_CTL1, TEST_IO Test Conditions 3.135V VDD 3.465V 3.135V VDD 3.465V Minimum 2 Typical Maximum VDD + 0.3 Units V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input High Current
VDD = VIN = 3.465V
5
µA
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
-150
µA
TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V±5%, TA = 0°C TO 85°C
Symbol VOH VOL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Test Conditions Minimum VDDO - 1.28 VDDO - 2.0 600 700 Typical Maximum VDDO - 0.980 VDDO - 1.7 850 Units V V mV
VSWING Peak-to-Peak Output Voltage Swing NOTE 1: Output terminated with 50 to VDDO - 2V.
ICS8431CM-01
www.icst.com/products/hiperclocks.html
3
REV. A JUNE 5, 2001
Others parts begin by ic
IC-1 IC-2 IC-3 IC-4 IC-5 IC-6 IC-7 IC-8 IC-9 IC-10 IC-11 IC-12 IC-13 IC-14 IC-15 IC-16 IC-17 IC-18 IC-19 IC-20 IC-21 IC-22 IC-23 IC-24 IC-25 IC-26 IC-27 IC-28
|
|
|
