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Part: ICS84314
Category:
Description:
Company: Integrated Circuit System
Datasheet: Download ICS84314 datasheet File size : 407 kB
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
FEATURES
· Fully integrated PLL · 4 differential 3.3V or 2.5V LVPECL outputs · Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK input · Output frequency range: 62.5MHz to 350MHz · VCO range: 250MHz to 700MHz · Parallel interface for programming counter and output dividers during power-up · Serial 3 wire interface · Full 3.3V and mixed 3.3V, 2.5V operating supply · 0°C to 70°C ambient operating temperature
GENERAL DESCRIPTION
The ICS84314 is a general purpose quad output f r e q u e n c y synthesizer and a member of the H iPerC lockSTM HiPerClockS family of High Performance Clock Solutions from ICS. When the device uses parallel loading, the M bits are programmable and the output divider is hard-wired for divide by 2 thus providing a frequency range of 125MHz to 350MHz. In serial programming mode, the M bits are programmable and the output divider can be set for either divide by 2 or divide by 4, providing a frequency range of 62.5MHz to 350MHz. The low cyclecycle jitter and broad frequency range of the ICS84314 make it an ideal clock generator for a variety of demanding applications which require high performance.
,&6
BLOCK DIAGRAM
PIN ASSIGNMENT
VCO_SEL nP_LOAD XTAL2 XTAL1 M3 M2 M1 M0
VCO_SEL 32 31 30 29 28 27 26 25 XTAL_SEL M4 TEST_CLK XTAL1 OSC XTAL2 ÷ 16 1 0 M5 M6 M7 M8 VEE VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3
24 23 22
TEST_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR VCCO
ICS84314
21 20 19 18 17
PLL
PHASE DETECTOR MR VCO ÷M ÷2 S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 0 1 ÷2 ÷4
VCCO Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3
CONFIGURATION INTERFACE LOGIC
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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1
REV. A MAY 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc. FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS84314 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A parallel-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a 16MHz crystal, this provides a 1MHz reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS84314 support two input modes to program the M divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the
ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
nP_LOAD input is initially LOW. The data on inputs M0 through M8 is passed directly to the M divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M bits can be hardwired to set the M divider to a specific default state that will automatically occur during power-up. In parallel mode, the N output divider is set to 2. In serial mode, the N output divider can be set for either ÷ 2 or ÷4. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fxtal x 2M fVCO = 16 The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 16MHz refere n c e are defined as 125 M 350. The frequency out is defined as follows: fout = fVCO x 1 = fxtal x 2M x 1 N N 16 Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK.
SERIAL LOADING
S_CLOCK
S_DATA S_LOAD
*NULL *NULL *NULL *NULL
t
S
**N
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
H
nP_LOAD
t
S
PARALLEL LOADING
M0:M8
M
nP_LOAD
t t
S
H
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS TABLE 1. N OUTPUT DIVIDER FUNCTION TABLE (SERIAL LOAD)
N Logic Value 0 1 Output Divide ÷2 ÷4
*NOTE: The NULL timing slot must be observed. **NOTE: "N" can only be controlled through serial loading.
84314AY
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2
REV. A MAY 16, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
Type Input Input Power Power Power Output Output Output Output Description
TABLE 2. PIN DESCRIPTIONS
Number 1, 2, 3, 4, 29, 30, 31, 32 5 6 7 8, 17 9, 10 11, 12 13, 14 15, 16 Name M4, M5, M6, M7, M0, M1, M2, M3 M8 VEE VCC VCCO Q0, nQ0 Q1, nQ1 Q2, nQ2 Q3, nQ3
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS / LVTTL interface levels. Pullup Negative supply pin. Core power supply pin.
Output supply pins. Differential output for the synthesizer. 3.3V LVPECL interface levels. Differential output for the synthesizer. 3.3V LVPECL interface levels. Differential output for the synthesizer. 3.3V LVPECL interface levels. Differential output for the synthesizer. 3.3V LVPECL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted 18 MR Input Pulldown outputs nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register 19 S_CLOCK Input Pulldown on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge 20 S_DATA Input Pulldown of S_CLOCK. LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the dividers. 21 S_LOAD Input Pulldown LVCMOS / LVTTL interface levels. 22 VCCA Power Analog supply pin. Selects between the crystal oscillator or test clock as the PLL 23 XTAL_SEL Input Pullup reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels. 24 TEST_CLK Input Pulldown Test clock input. LVCMOS / LVTTL interface levels. 25, 26 XTAL1, XTAL2 Input Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Parallel load input. Determines when data present at M8:M0 27 nP_LOAD Input Pulldown is loaded into the M divider. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. 28 VCO_SEL Input Pullup LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
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REV. A MAY 16, 2003
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