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Details, datasheet, quote on part number:ICS85314-11I
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS85314I-11
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
FEATURES
· 5 differential 2.5V/3.3V LVPECL outputs · Selectable differential CLKx, nCLKx inputs · CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL · Maximum output frequency: 700MHz · Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input · Output skew: 30ps (maximum) · Part-to-part skew: 250ps (maximum) · Propagation delay: 1.8ns (maximum) · LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V · -40°C to 85°C ambient operating temperature · Compatible to part number MC100LVEP14
GENERAL DESCRIPTION
The ICS85314I-11 is a low skew, high performance 1-to-5 Differential-to-2.5V/3.3V LVPECL H iPerC lockSTM fanout buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS85314I-11 has two selectable differential clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt clock p u l s e s on the outputs during asynchronous assertion/ deassertion of the clock enable pin.
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Guaranteed output and part-to-part skew characteristics make the ICS85314I-11 ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
nCLK_EN D Q CK CLK0 nCLK0 CLK1 nCLK1 CLK_SEL Q2 nQ2 Q3 nQ3 Q4 nQ4
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC nCLK_EN VCC nCLK1 CLK1 RESER VED nCLK0 CLK0 CLK_SEL VEE
00 1
1
Q0 nQ0 Q1 nQ1
ICS85314I-11
20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm Package Body G Package Top View
ICS85314I-11
20-Lead SOIC 7.5mm x 12.8mm x 2.3mm Package Body M Package Top View
85314AGI-11
www.icst.com/products/hiperclocks.html
1
REV. A JUNE 11, 2003
Integrated Circuit Systems, Inc.
ICS85314I-11
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Type Description Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Negative supply pin. Clock select input. When HIGH, selects SCLK input. Pulldown When LOW, selects CLK, nCLK inputs. LVTTL / LVCMOS interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Do not connect. Input Input Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 6 7, 8 9, 10 11 12 13 14 15 16 17 18, 20 Name Q0, nQ0 Q1, nQ1 Q2, nQ2 Q3, nQ3 Q4, nQ4 VEE CLK_SEL CLK0 nCLK0 RESERVED CLK1 nCLK1 VCC Output Output Output Output Output Power Input Input Input
Positive supply pins. Synchronizing clock enable. When LOW, clock outputs follow clock 19 nCLK_EN Input Pulldown input. When HIGH, Q outputs are forced low, nQ outputs are forced high. LVTTL / LVCMOS interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Power
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
85314AGI-11
www.icst.com/products/hiperclocks.html
2
REV. A JUNE 11, 2003
Integrated Circuit Systems, Inc.
ICS85314I-11
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
Inputs Outputs Selected Source CLK0, nCLK0 CLK1, nCLK1 CLK0, nCLK0 Q0:Q4 Enabled Enabled Disabled; LOW nQ0:nQ4 Enabled Enabled Disabled; HIGH
TABLE 3A. CONTROL INPUT FUNCTION TABLE
nCLK_EN 0 0 1 CLK_SEL 0 1 0
1 1 CLK1, nCLK1 Disabled; LOW Disabled; HIGH After nCLK_EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1, nCLK1 inputs as described in Table 3B.
Disabled
nCLK0, nCLK1 CLK0, CLK1
Enabled
nCLK_EN
nQ0:nQ4 Q0:Q4
FIGURE 1. nCLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK0 or CLK1 0 1 nCLK0 or nCLK1 1 0 Q0:Q4 LOW HIGH Outputs nQ0:nQ4 HIGH LOW Input to Output Mode Differential to Differential Differential to Differential Polarity Non Inver ting Non Inver ting
85314AGI-11
www.icst.com/products/hiperclocks.html
3
REV. A JUNE 11, 2003
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