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Details, datasheet, quote on part number:ICS8532
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS8532-01
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
FEATURES
· 17 differential 3.3V LVPECL outputs · Selectable differential CLK, nCLK or LVPECL clock inputs · CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL · PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL · Maximum output frequency: 500MHz · Translates any single-ended input signal (LVCMOS, LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on nCLK input · Output skew: 50ps (maximum) · Part-to-part skew: 250ps (maximum) · Propagation delay: 2.5ns (maximum) · 3.3V operating supply · 0°C to 70°C ambient operating temperature · Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8532-01 is a low skew, 1-to-17, Differe n t i a l - t o - 3 . 3 V LVPECL Fanout Buffer and a H iPerC lockSTM member of the HiPerClockSTM family of High Perf o r m a n c e Clock Solutions from ICS. The ICS8532-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
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Guaranteed output and part-to-part skew characteristics make the ICS8532-01 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_EN D Q CLK nCLK PCLK nPCLK CLK_SEL
PIN ASSIGNMENT
VCCO nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 Q0 Q1 Q2 Q3 Q4 Q5
LE 0 1
Q0:Q16 nQ0:nQ16
V CCO nc nc VCC CLK nCLK CLK_SEL PCLK nPCLK VEE CLK_EN VEE V CCO
1 2 3 4 5 6 7 8 9
5 2 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
VCCO Q6 nQ6 Q7 nQ7 Q8 nQ8 VCCO Q9 nQ9 Q10 nQ10 VCCO
ICS8532-01
33 32 31 30 29 28
10 11 12
27 13 1 4 15 16 17 18 19 20 21 22 23 24 25 26
nQ16 Q16 nQ15 Q15 nQ14 Q14 V CCO nQ13 Q13 nQ12 Q12 nQ11 Q11
52-Lead LQFP 10mm x 10mm x 1.4mm body package Y package Top View
8532AY-01
www.icst.com/products/hiperclocks.htlm
1
REV. B MAY 28, 2002
Integrated Circuit Systems, Inc.
ICS8532-01
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Type Description Output supply pins. No connect. Positive supply pins. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When HIGH, selects CLK, nCLK inputs. Pulldown When LOW, selects PCLK, nPCLK inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential LVPECL clock input. Pullup Inver ting differential LVPECL clock input. Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follows clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Pullup
TABLE 1. PIN DESCRIPTIONS
Number 1, 13, 20, 27, 32, 39, 46 2, 3 4 5 6 7 8 9 10, 12 11 14, 15 16, 17 18, 19 Name VCCO nc VCC CLK nCLK CLK_SEL PCLK nPCLK VEE CLK_EN nQ16, Q16 nQ15, Q15 nQ14, Q14 Power Unused Power Input Input Input Input Input Power Input Output Output Output
Pullup
21, 22 nQ13, Q13 Output Differential clock outputs. LVPECL interface levels. 23, 24 nQ12, Q12 Output Differential clock outputs. LVPECL interface levels. 25, 26 nQ11, Q11 Output Differential clock outputs. LVPECL interface levels. 28, 29 nQ10, Q10 Output Differential clock outputs. LVPECL interface levels. 30, 31 nQ9, Q9 Output Differential clock outputs. LVPECL interface levels. 33, 34 nQ8, Q8 Output Differential clock outputs. LVPECL interface levels. 35, 36 nQ7, Q7 Output Differential clock outputs. LVPECL interface levels. 37, 38 nQ6, Q6 Output Differential clock outputs. LVPECL interface levels. 40, 41 nQ5, Q5 Output Differential clock outputs. LVPECL interface levels. 42, 43 nQ4, Q4 Output Differential clock outputs. LVPECL interface levels. 44, 45 nQ3, Q3 Output Differential clock outputs. LVPECL interface levels. 47, 48 nQ2, Q2 Output Differential clock outputs. LVPECL interface levels. 49, 50 nQ1, Q1 Output Differential clock outputs. LVPECL interface levels. 51, 52 nQ0, Q0 Output Differential clock outputs. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. NOTE: Unused output pairs must be terminated.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter CLK, nCLK Input Capacitance PCLK, nPCLK CLK_EN, CLK_SEL Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 4 4 Units pF pF pF K K
8532AY-01
www.icst.com/products/hiperclocks.htlm
2
REV. B MAY 28, 2002
Integrated Circuit Systems, Inc.
ICS8532-01
LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Inputs Outputs Selected Source CLK, nCLK PCLK, nPCLK CLK, nCLK Q0:Q16 Disabled; LOW Disabled; LOW Enabled nQ0:nQ16 Disabled; HIGH Disabled; HIGH Enabled
TABLE 3A. CONTROL INPUT FUNCTION TABLE
CLK_EN 0 0 1 CLK_SEL 0 1 0
1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B.
Disabled
nCLK, nPCLK CLK, PCLK
Enabled
CLK_EN
nQ0:nQ16 Q0:Q16
FIGURE 1 - CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK or PCLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK or nPCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q16 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0:nQ16 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section "Wiring the Differential Input to Accept Single Ended Levels".
8532AY-01
www.icst.com/products/hiperclocks.htlm
3
REV. B MAY 28, 2002
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