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Details, datasheet, quote on part number:ICS85322AM
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS85322
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
FEATURES
· 2 differential 2.5V/3.3V LVPECL outputs · Selectable CLK0, CLK1 LVCMOS/LVTTL clock inputs · CLK0 and CLK1 can accepts the following input levels: LVCMOS or LVTTL · Maximum output frequency: 267MHz · Part-to-part skew: 250ps (maximum) · 3.3V operating supply voltage (operating range 3.135V to 3.465V) · 2.5V operating supply voltage (operating range 2.375V to 2.625V) · 0°C to 70°C ambient operating temperature · Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS85322 is a Dual LVCMOS / LVTTL-toDifferential 2.5V / 3.3V LVPECL translator and a H iPerC lockSTM member of the HiPerClocksTM family of High Perf o r m a n c e Clocks Solutions from ICS. The ICS85322 has selectable single ended clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and translate them to 2.5V / 3.3V LVPECL levels. The small outline 8-pin SOIC package makes this device ideal for applications where space, high performance and low power are important.
,&6
BLOCK DIAGRAM
CLK0 Q0 nQ0 Q1 nQ1
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 VCC CLK0 CLK1 VEE
CLK1
ICS85322
8-Lead SOIC 3.90mm x 4.92mm x 1.37mm body package M Package Top View
85322AM
www.icst.com/products/hiperclocks.html
1
REV. B JUNE 12, 2003
Integrated Circuit Systems, Inc.
ICS85322
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
Type Output Output Power Input Input Power Pullup Pullup Description Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Negative supply pin. LVCMOS / LVTTL clock input. LVCMOS / LVTTL clock input. Positive supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5 6 7 8 Name Q0, nQ0 Q1, nQ1 VEE CLK1 CLK0 VCC
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
85322AM
www.icst.com/products/hiperclocks.html
2
REV. B JUNE 12, 2003
Integrated Circuit Systems, Inc.
ICS85322
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
4.6V -0.5V to VCC + 0.5 V 50mA 100mA 112.7°C/W (0 lfpm) -65°C to 150°C N O T E : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI O u t p u t s , IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 25 Units V mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK0, CLK1 CLK0, CLK1 CLK0, CLK1 CLK0, CLK1 VCC = VIN = 3.465V VCC = VIN = 3.465V -150 Test Conditions Minimum 2 -0.3 Typical Maximum 3.765 1.3 5 Units V V µA µA
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter VOH VOL VSWING Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V Minimum VCC - 1.4 VCC - 2.0 0.65 Typical Maximum VCC - 1.0 VCC - 1.7 0.9 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 4A. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 Output Rise/Fall Time 20% to 80% @ 50MHz 300 267MHz 0.6 Test Conditions Minimum Typical Maximum 267 1.8 250 700 60 Units MHz ns ps ps %
t sk(pp)
tR / tF
odc Output Duty Cycle 40 All parameters measured at 133MHz unless noted otherwise. NOTE 1: Measured from VCC/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
85322AM
www.icst.com/products/hiperclocks.html
3
REV. B JUNE 12, 2003
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