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Details, datasheet, quote on part number:ICS8533
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS8533-01
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
FEATURES
· 4 differential 3.3V LVPECL outputs · Selectable differential CLK, nCLK or LVPECL clock inputs · CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL · PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL · Maximum output frequency: 650MHz · Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input · Output skew: 30ps (maximum) · Part-to-part skew: 150ps (maximum) · Propagation delay: 1.4ns (maximum) · 3.3V operating supply · 0°C to 70°C ambient operating temperature · Industrial temperature information available upon request
GENERAL DESCRIPTION
T h e ICS8533-01 is a low skew, high performance 1-to-4 Differential-to-3.3V LVPECL fanout H iPerC lockSTM buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8533-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
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G u a r a n t e e d output and part-to-part skew characteristics make the ICS8533-01 ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_EN D Q LE CLK nCLK PCLK nPCLK 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3
PIN ASSIGNMENT
VEE CLK_EN CLK_SEL CLK nCLK PCLK nPCLK nc nc VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VCC Q1 nQ1 Q2 nQ2 VCC Q3 nQ3
CLK_SEL
ICS8533-01
20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View
8533AG-01
www.icst.com/products/hiperclocks.html
1
REV. C OCTOBER 3, 2002
Integrated Circuit Systems, Inc.
ICS8533-01
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Type Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8, 9 10, 13, 18 11, 12 14, 15 16, 17 19, 20 Name VEE CLK_EN CLK_SEL CLK nCLK PCLK nPCLK nc VCC nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 Power Input Input Input Input Input Input Unused Power Output Output Output Output Negative supply pin. Synchronizing clock enable. When HIGH, clock outputs follow clock input. Pullup When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects differential PCLK, nPCLK inputs. Pulldown When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Pullup Inver ting differential clock input. Inver ting differential LVPECL clock input. No connect. Positive supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Pulldown Non-inver ting differential LVPECL clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
8533AG-01
www.icst.com/products/hiperclocks.html
2
REV. C OCTOBER 3, 2002
Integrated Circuit Systems, Inc.
ICS8533-01
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Inputs Outputs Selected Source CLK, nCLK PCLK, nPCLK CLK, nCLK Q0:Q3 Disabled; LOW Disabled; LOW Enabled nQ0:nQ3 Disabled; HIGH Disabled; HIGH Enabled
TABLE 3A. CONTROL INPUT FUNCTION TABLE
CLK_EN 0 0 1 CLK_SEL 0 1 0
1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described in Table 3B.
Disabled
nCLK, nPCLK CLK, PCLK
Enabled
CLK_EN
nQ0:nQ3 Q0:Q3
FIGURE 1 - CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK or PCLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK or nPCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q3 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0:nQ3 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
8533AG-01
www.icst.com/products/hiperclocks.html
3
REV. C OCTOBER 3, 2002
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