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Details, datasheet, quote on part number:ICS8534
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Datasheet text preview:
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
FEATURES
· 22 differential LVPECL outputs each with the ability to drive 50 to ground · Selectable differential CLK, nCLK or LVPECL clock inputs · CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL · PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL · Maximum output frequency: 500MHz · Translates any single-ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input · 3.3V supply mode · 0°C to 85°C ambient operating temperature
GENERAL DESCRIPTION
The ICS8534-01 is a low skew, 1-to-22 Differential-to-3.3V LVPECL Fanout Buffer and a member H iPer Cl ockSTM of the HiPerClockSTM Family of High Performance Clock Solutions from ICS. The ICS8534-01 has two selectable clock inputs. The CLK, nCLK pair c a n accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. Its CLK_SEL pin selects the input which can be either LVHSTL or LVPECL. The device is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the OE pin. The ICS8534-01's low output and part-to-part skew characteristics make it ideal for workstation, server, and other high performance clock distribution applications.
,&6
BLOCK DIAGRAM
CLK_SEL CLK nCLK PCLK nPCLK
PIN ASSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 25 57 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VC C O nQ13 Q13 nQ12 Q12 nQ11 Q11 nQ10 Q10 nQ9 Q9 nQ8 Q8 nQ7 Q7 VC C O
0
22 22
Q0:Q21 nQ0:nQ21
1 LE Q
OE
D
VCCO nQ6 Q6 nQ5 Q5 nQ4 Q4 nQ3 Q3 nQ2 Q2 nQ1 Q1 nQ0 Q0 VCCO
ICS8534-01
VC C O Q14 nQ14 Q15 nQ15 Q16 nQ16 Q17 nQ17 Q18 nQ18 Q19 nQ19 Q20 nQ20 VC C O
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8534AY-01 www.icst.com/products/hiperclocks.html REV. A JANUARY 20, 2003
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VC C O nc nc VCC CLK nCLK CLK_SEL PCLK nPCLK VEE OE nc nc nQ21 Q21 VC C O
64-Lead TQFP E-Pad 10mm x 10mm x 1.0mm package body Y package Top View
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Type Power Unused Power Input Input Input Input Input Input Input Output Output Output Output Output Pullup Description Output supply pins. No connect. Core supply pin. Pulldown Non-inver ting differential clock input pair. Inver ting differential clock input pair. Pulled to 2/3 VCC. Clock select input. When HIGH, selects PCLK, nPCLK inputs. Pullup When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential LVPECL clock input pair. Inver ting differential LVPECL clock input pair. Pulled to 2/3 VCC. Power supply ground. Output enable. Controls enabling and disabling of outputs Q0:Q21, nQ0:nQ21. LVCMOS / LVTTL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 16, 17, 32, 33, 48, 49, 64 2, 3, 12, 13 4 5 6 7 8 9 10 11 14, 15 18, 19 20, 21 22, 23 24, 25 26, 27 28, 29 30, 31 34, 35 36, 37 38, 39 40, 41 42, 43 44, 45 46, 47 50, 51 52, 53 54, 55 56, 57 58, 59 60, 61 62, 63 NOTE: Pullup and Name VCCO nc VCC CLK nCLK CLK_SEL PCLK nPCLK VEE OE nQ21, Q21 nQ20, Q20 nQ19, Q19 nQ18, Q18 nQ17, Q17 nQ16, Q16 nQ15, Q15 nQ14, Q14 nQ13, Q13 nQ12, Q12 nQ11, Q11 nQ10, Q10 nQ9, Q9 nQ8, Q8 nQ7, Q7 nQ6, Q6 nQ5, Q5 nQ4, Q4 nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 Pulldown refer
Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8534AY-01
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 20, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Test Conditions Minimum Typical 37 75 Maximum 4 Units pF K K
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor
TABLE 3. CONTROL INPUT FUNCTION TABLE
Inputs OE 0 0 1 1 CLK_SEL 0 1 0
1
Q0:Q21 LOW LOW CLK PCLK
Outputs nQ0:nQ21 HIGH HIGH nCLK nPCLK
Disabled
nCLK, nPCLK CLK, PCLK
Enabled
OE
nQ0 :nQ21 Q0 :Q21
FIGURE 1. OE TIMING DIAGRAM
8534AY-01
www.icst.com/products/hiperclocks.html
3
REV. A JANUARY 20, 2003
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