|
Details, datasheet, quote on part number:ICS8535-01I
| |
Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS8535I-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
FEATURES
· 4 differential 3.3V LVPECL outputs · Selectable LVCMOS / LVTTL clock inputs for redundant and multiple frequency fanout applications · Maximum output frequency: 266MHz · Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels · Output skew: 30ps (maximum) · Part-to-part skew: 250ps (maximum) · 3.3V operating supply · -40°C to 85°C ambient operating temperature
GENERAL DESCRIPTION
T h e ICS8535I-01 is a low skew, high performance 1-to-4 LVCMOS-to-3.3V LVPECL fanout H iPerC lockSTM buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8535I-01 has two selectable clock inputs that accept LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
,&6
G u a r a n t e e d output and part-to-part skew characteristics make the ICS8535I-01 ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_EN D Q LE CLK0 CLK1 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3
PIN ASSIGNMENT
VEE CLK_EN CLK_SEL CLK0 nc CLK1 nc nc nc VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VCC Q1 nQ1 Q2 nQ2 VCC Q3 nQ3
CLK_SEL
ICS8535I-01
20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View
8535AGI-01
www.icst.com/products/hiperclocks.html
1
REV. C JANUARY 20, 2003
Integrated Circuit Systems, Inc.
ICS8535I-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Type Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 6 5, 7, 8, 9 10, 13, 18 11, 12 14, 15 16, 17 19, 20 NOTE: Pullup Name VEE CLK_EN CLK_SEL CLK0 CLK1 nc VCC Power Input Input Input Input Unused Power Negative supply pin. Synchronizing clock enable. When HIGH, clock outputs follow clock input. Pullup When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK1 input. Pulldown When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. Pulldown LVCMOS / LVTTL clock input. Pulldown LVCMOS / LVTTL clock input. No connect. Positive supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. resistors. See Table 2, Pin Characteristics, for typical values.
nQ3, Q3 Output nQ2, Q2 Output nQ1, Q1 Output nQ0, Q0 Output and Pulldown refer to internal input
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
8535AGI-01
www.icst.com/products/hiperclocks.html
2
REV. C JANUARY 20, 2003
Integrated Circuit Systems, Inc.
ICS8535I-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Inputs Outputs Selected Source CLK0 CLK1 CLK0 Q0:Q3 Disabled; LOW Disabled; LOW Enabled nQ0:nQ3 Disabled; HIGH Disabled; HIGH Enabled
TABLE 3A. CONTROL INPUT FUNCTION TABLE
CLK_EN 0 0 1 CLK_SEL 0 1 0
1 1 CLK1 Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 1. In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3B.
Disabled
CLK0, CLK1
Enabled
CLK_EN
nQ0:nQ3 Q0:Q3
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK0 or CLK1 0 1 Q0:Q3 LOW HIGH Outputs nQ0:nQ3 HIGH LOW
8535AGI-01
www.icst.com/products/hiperclocks.html
3
REV. C JANUARY 20, 2003
|
|
