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Details, datasheet, quote on part number:ICS8535-11I
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS8535I-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
FEATURES
· 4 differential 3.3V LVPECL outputs · Selectable CLK or crystal inputs · CLK can accept the following input levels: LVCMOS, LVTTL · Maximum output frequency: 266MHz · Output skew: 40ps (maximum) · Part-to-part skew: 250ps (maximum) · 3.3V operating supply · -40°C to 85°C ambient operating temperature
GENERAL DESCRIPTION
The ICS8535I-11 is a low skew, high performance 1-to-4 3.3V LVPECL clock fanout buffer and a H iPerC lockSTM m e m b e r of the HiPerClockSTM family of High P e r f o r m a n c e Clock Solutions from ICS. The ICS8535I-11 has selectable single ended clock o r crystal inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
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G u a r a n t e e d output and part-to-part skew characteristics make the ICS8535I-11 ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_EN D Q LE CLK XTAL1 XTAL2 CLK_SEL 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3
PIN ASSIGNMENT
VEE CLK_EN CLK_SEL CLK nc XTAL1 XTAL2 nc nc VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VCC Q1 nQ1 Q2 nQ2 VCC Q3 nQ3
ICS8535I-11
20-Lead TSSOP 6.5mm x 4.4mm x 0.92 package body G Package Top View
8535AGI-11
www.icst.com/products/hiperclocks.html
1
REV. C JANUARY 16, 2003
Integrated Circuit Systems, Inc.
ICS8535I-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Type Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5, 8, 9 6, 7 10, 13, 18 11, 12 14, 15 16, 17 19, 20 Name VEE CLK_EN CLK_SEL CLK nc XTAL1, XTAL2 VCC nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 Power Input Input Input Unused Input Power Output Output Output Output Negative supply pin. Synchronizing clock enable. When HIGH, clock outputs follows clock Pullup input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects XTAL inputs. Pulldown When LOW, selects CLK input. LVCMOS / LVTTL interface levels. Pulldown Clock input. LVCMOS / LVTTL interface levels. No connect. Cr ystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Positive supply pins. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
8535AGI-11
www.icst.com/products/hiperclocks.html
2
REV. C JANUARY 16, 2003
Integrated Circuit Systems, Inc.
ICS8535I-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Inputs Outputs Selected Source CLK XTAL1, XTAL2 CL K Q0:Q3 Disabled; LOW Disabled; LOW Enabled nQ0:nQ3 Disabled; HIGH Disabled; HIGH Enabled Enabled
TABLE 3A. CONTROL INPUT FUNCTION TABLE
CLK_EN 0 0 1 CLK_SEL 0 1 0
1 1 XTAL1, XTAL2 Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock or cr ystal oscillator edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK input as described in Table 3B.
Disabled
CLK
Enabled
CLK_EN
nQ0:nQ3 Q0:Q3
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK 0 1 Q0:Q3 LOW HIGH Outputs nQ0:nQ3 HIGH LOW
8535AGI-11
www.icst.com/products/hiperclocks.html
3
REV. C JANUARY 16, 2003
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