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Details, datasheet, quote on part number:ICS87949-01I
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Datasheet text preview:
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS87949I-01
LOW SKEW, ÷1, ÷2 CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87949I-01 is a low skew, ÷1, ÷2 Clock Generator and a member of the HiPerClockSTM H iPer Cl ockSTM family of High Performance Clock Solutions from ICS. The ICS87949I-01 has selectable single ended clock or LVPECL clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 15 to 30 by utilizing the ability of the outputs to drive two series terminated lines.
FEATURES
· 15 single ended LVCMOS outputs, 7 typical output impedance · Selectable LVCMOS or LVPECL clock inputs · CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL · PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL · Maximum input frequency: 250MHz · Output skew: 200ps (maximum) · Part-to-part skew: 500ps (typical) · Multiple frequency skew: 350ps (maximum) · 3.3V input, outputs may be either 3.3V or 2.5V supply modes · -40°C to 85°C ambient operating temperature · Functionally compatible to the MPC949 in a smaller footprint requiring less board space
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The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master reset input, MR/ nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. The ICS87949I-01 is characterized at 3.3V core/3.3V output and 3.3V core/ 2.5V output. Guaranteed bank, output and partto-part skew characteristics make the ICS87949I-01 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_SEL CLK0 CLK1 PCLK nPCLK PCLK_SEL 1 DIV_SELA 0 QB0:QB2 1 DIV_SELB 0 QC0:QC3 1 DIV_SELC 0 QD0:QD5 1 DIV_SELD MR/nOE 0 0 1 1 ÷1 ÷2 R 0 QA0:QA1
PIN ASSIGNMENT
GND GND GND GND VDDB VDDA VDDB QA0 QA1 QB0 QB1 QB2
4 8 47 46 45 44 43 42 41 40 39 38 37 MR/nOE CLK_SEL VDD CLK0 CLK1 PCLK nPCLK PCLK_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 18 19 20 21 22 23 24
GND GND QD0 V DDD QD1 GND QD2 V DDD QD3 GND QD4 V DDD
36 35 34 33 32 31 30 29 28 27 26 25
nc GND QC0 V DDC QC1 GND QC2 V DDC QC3 GND GND QD5
ICS87949I-01
48-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 87949AYI-01 www.icst.com/products/hiperclocks.html REV. A AUGUST 16, 2002
1
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS87949I-01
LOW SKEW ÷1, ÷2 CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4, 5 6 7 8 9 10 11 12 13, 14, 18, 22, 26, 27, 31, 35, 39, 43, 44, 48 15, 17, 19, 21, 23, 25 16, 20, 24, 28, 30, 32, 34 29, 33 36 37, 41 38, 40, 42 45, 47 46 Name MR/nOE CLK_SEL VDD CLK0, CLK1 PCLK nPCLK PCLK_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD Input Input Power Input Input Input Input Input Input Input Input Type Description Master Reset and output enable. When LOW, output drivers are Pulldown enabled. When HIGH, output drivers are in HiZ and dividers are reset. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK1. Pulldown When LOW, selects CLK0. LVCMOS / LVTTL interface levels. Positive supply pin. Pullup Pullup LVCMOS / LVTTL clock inputs. Inver ting differential LVPECL clock input. A outputs. B outputs. C outputs. D outputs. Pulldown Non-inver ting differential LVPECL clock input. Pulldown PCLK select input. Controls frequency division for Bank Pulldown LVCMOS / LVTTL interface levels. Controls frequency division for Bank Pulldown LVCMOS / LVTTL interface levels. Controls frequency division for Bank Pulldown LVCMOS / LVTTL interface levels. Controls frequency division for Bank Pulldown LVCMOS / LVTTL interface levels. Power supply ground.
GND QD0, QD1, QD2, QD3, QD4, QD5 VDDD QC3, QC2, QC1, QC0 VDDC nc VDDB QB2, QB1, QB0 QA1, QA0 VDDA
Power
Output Power Output Power Unused Power Output Output Power
Bank D outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Positive supply pins for Bank D outputs. Bank C outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Positive supply pins for Bank C outputs. No connect. Positive supply pins for Bank B outputs. Bank B outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Bank A outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Positive supply pins for Bank A outputs.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87949AYI-01
www.icst.com/products/hiperclocks.html
2
REV. A AUGUST 16, 2002
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS87949I-01
LOW SKEW, ÷1, ÷2 CLOCK GENERATOR
Maximum 4 51 51 Units pF K K pF
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output); NOTE 1 Output Impedance Test Conditions Minimum Typical
VDD, *VDDx = 3.465V
TBD 7
NOTE 1: VDDx denotes VDDA, VDDB, VDDC, VDDD.
TABLE 3. FUNCTION TABLE
MR/nOE 1 0 0 0 0 0 0 0 0 DIV_SELA X 0 1 X X X X X X Inputs DIV_SELB X X X 0 1 X X X X DIV_SELC X X X X X 0 1 X X DIV_SELD X X X X X X X 0 1 QA0:QA1 Hi Z fIN/1 fIN/2 Active Active Active Active Active Active Outputs QB0:QB2 QC0:QC3 Hi Z Hi Z Active Active Active Active fIN/1 Active fIN/2 Active Active fIN/1 Active fIN/2 Active Active Active Active QD0:QD5 Hi Z Active Active Active Active Active Active fIN/1 fIN/2
87949AYI-01
www.icst.com/products/hiperclocks.html
3
REV. A AUGUST 16, 2002
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