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Details, datasheet, quote on part number:ICS87949I
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| Part: | ICS87949I |
| Category: | Timing Circuits => Clock Buffers => Dividers |
| Description: | Lowskew Divide-by-1, Divide-by-2 Clock Generator. Pin Compatible WithMPC949. Industrial Temperature. |
| Company: | Integrated Circuit System |
| Datasheet: | Download ICS87949I datasheet File size : 118 kB |
| Request For quote: | Find where to buy ICS87949I
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Datasheet text preview:
Integrated Circuit Systems, Inc.
LOW SKEW, ÷1, ÷2 CLOCK GENERATOR
FEATURES
· 15 single ended LVCMOS outputs, 7 typical output impedance · Selectable LVCMOS or LVPECL clock inputs · CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL · PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL · Maximum output frequency: 160MHz · Output skew: 350ps (maximum) · Part-to-part skew: 2.75ns (maximum) · 3.3V supply voltage · -40°C to 85°C ambient operating temperature · Pin compatible to the MPC949
ICS87949I
GENERAL DESCRIPTION
The ICS87949I is a low skew, ÷1, ÷2 Clock Generator and a member of the HiPerClockSTM family H iPer Cl ockSTM o f High Performance Clock Solutions from ICS. The ICS87949I has selectable single ended clock or LVPECL clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 15 to 30 by utilizing the ability of the outputs to drive two series terminated lines.
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The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master reset input, MR/nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. The ICS87949I is characterized at 3.3V core/3.3V output. Guaranteed output and part-to-part skew characteristics make the ICS87949I ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_SEL CLK0 CLK1 PCLK nPCLK PCLK_SEL 1 DIV_SELA 0 QB0:QB2 1 DIV_SELB 0 QC0:QC3 1 DIV_SELC 0 QD0:QD5 1 DIV_SELD MR/nOE 0 0 1 1 ÷1 ÷2 R 0 QA0:QA1
PIN ASSIGNMENT
GND GND GND GND VDDB VDDA VDDB QA0 QA1 QB0 QB1 QB2 nc
MR/nOE CLK_SEL VDD CLK0 CLK1 PCLK nPCLK PCLK_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD GND
1 2 3 4 5 6 7 8 9
5 2 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
nc GND QC0 V DDC QC1 GND QC2 V DDC QC3 GND GND QD5 nc
ICS87949I
33 32 31 30 29 28
10 11 12
13 27 1 4 15 16 17 18 19 20 21 22 23 24 25 26
nc GND QD0 VD D D QD1 GND QD2 VD D D QD3 GND QD4 VD D D nc
52-Lead LQFP 10mm x 10mm x 1.4mm package body Y Package Top View
87949AYI
www.icst.com/products/hiperclocks.html
1
REV. B NOVEMBER 21, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, ÷1, ÷2 CLOCK GENERATOR
Type Input Input Power Input Input Input Input Input Input Input Input Power Unused Output Power Output Power Power Output Output Power Description Master reset and output enable When LOW, output drivers are Pulldown enabled. When HIGH, output drivers are in HiZ and dividers are reset. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK1. When LOW, Pulldown selects CLK0. LVCMOS / LVTTL interface levels. Core supply pin. Pullup Pullup LVCMOS / LVTTL clock inputs. Inver ting differential LVPECL clock input.
ICS87949I
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4, 5 6 7 8 9 10 11 12 13, 15, 19, 23, 29, 30, 34, 38, 43, 47, 48, 52 14, 26, 27, 39, 40 16, 18, 20, 22, 24, 28 17, 21, 25 31, 33, 35, 37 32, 36 41, 45 42, 44, 46 49, 51 50 Name MR/nOE CLK_SEL VDD CLK0, CLK1 PCLK nPCLK PCLK_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD GND nc QD0, QD1, QD2, QD3, QD4, QD5 VDDD QC3, QC2, QC1, QC0 VDDC VDDB QB2, QB1, QB0 QA1, QA0 VDDA
Pulldown Non-inver ting differential LVPECL clock input. Pulldown PCLK select input. LVCMOS / LVTTL interface levels. Controls frequency division for Bank A outputs. Pulldown LVCMOS / LVTTL interface levels. Controls frequency division for Bank B outputs. Pulldown LVCMOS / LVTTL interface levels. Controls frequency division for Bank C outputs. Pulldown LVCMOS / LVTTL interface levels. Controls frequency division for Bank D outputs. Pulldown LVCMOS / LVTTL interface levels. Power supply ground. No connect. Bank D outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Positive supply pins for Bank D outputs. Bank C outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Positive supply pins for Bank C outputs. Positive supply pins for Bank B outputs. Bank B outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Bank A outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Positive supply pins for Bank A outputs.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87949AYI
www.icst.com/products/hiperclocks.html
2
REV. B NOVEMBER 21, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, ÷1, ÷2 CLOCK GENERATOR
Test Conditions Minimum Typical 51 51 25 7 Maximum 4 Units pF K K pF
ICS87949I
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output); Output Impedance
TABLE 3. FUNCTION TABLE
MR/nOE 1 0 0 0 0 0 0 0 0 DIV_SELA X 0 1 X X X X X X Inputs DIV_SELB X X X 0 1 X X X X DIV_SELC X X X X X 0 1 X X DIV_SELD X X X X X X X 0 1 QA0, QA1 Hi Z fIN/1 fIN/2 Active Active Active Active Active Active Outputs QB0:QB2 QC0:QC3 Hi Z Hi Z Active Active Active Active fIN/1 Active fIN/2 Active Active fIN/1 Active fIN/2 Active Active Active Active QD0:QD5 Hi Z Active Active Active Active Active Active fIN/1 fIN/2
87949AYI
www.icst.com/products/hiperclocks.html
3
REV. B NOVEMBER 21, 2002
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