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Details, datasheet, quote on part number:ICS87951AYI
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| Part: | ICS87951AYI |
| Category: | Timing Circuits => Clock Buffers => Zero Delay Fanout |
| Description: | Lowskew 1-to-9 Clock Generator. Pin Compatible With MPC951. Industrialtemperature. |
| Company: | Integrated Circuit System |
| Datasheet: | Download ICS87951AYI datasheet File size : 144 kB |
| Request For quote: | Find where to buy ICS87951AYI
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS87951I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
FEATURES
· Fully integrated PLL · 9 single ended 3.3V LVCMOS outputs · Selectable single ended CLK0 or differential CLK1, nCLK1 inputs · The single ended CLK0 input can accept the following input levels: LVCMOS or LVTTL input levels · CLK1, nCLK1 supports the following input types: LVDS, LVPECL, LVHSTL, SSTL, HCSL · Output frequency range: 25MHz to 180MHz · VCO range: 200MHz to 480MHz · External feedback for "zero delay" clock regeneration · Cycle-to-cycle jitter: ±100ps (typical) · Output skew: 375ps (maximum) · PLL reference zero delay: 350ps window (maximum) · 3.3V operating supply · -40°C to 85°C ambient operating temperature · Pin compatible with the MPC951
GENERAL DESCRIPTION
The ICS87951I is a low voltage, low skew 1-to-9 Differential-to-LVCMOS clock generator and a H iPerC lockSTM member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS87951I has two selectable clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels. The CLK1, nCLK1 pair can accept most standard differential input levels. With output frequencies up to 180MHz, the ICS87951I is targeted for high performance clock applications. Along with a fully integrated PLL, the ICS87951I contains frequency configurable outputs and an external feedback input for regenerating clocks with "zero delay".
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PIN ASSIGNMENT
CLK_SEL PLL_SEL CLK0 GND GND VDDO QB QA
32 31 30 29 28 27 26 25 VDDA EXT_FB DIV_SELA DIV_SELB DIV_SELC DIV_SELD GND CLK1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 QC0 V DDO QC1 GND QD0 V DDO QD1 GND
ICS87951I
21 20 19 18 17
7mm x 7mm x 1.4mm package body Y package Top View
nCLK1
MR/nOE
32-Lead LQFP
VDDO
QD4
GND
QD3
VDDO
QD2
87951AYI
www.icst.com/products/hiperclocks.html
1
REV. A APRIL 15, 2002
Integrated Circuit Systems, Inc.
ICS87951I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
BLOCK DIAGRAM
DIV_SELA Internal Pulldown P L L _ S E L Internal Pulldown C L K 0 Internal Pulldown CLK_SEL
Internal Pulldown
nCLK1 CLK1
Internal Pulldown/ Pullup
1 0 PHASE DETECTOR VCO 200-480MHz 0 1
÷2 ÷4 ÷8
0
QA
1
0 LPF 1
EXT _FB Internal Pullup DIV_SELB Internal Pulldown QB
0 1
QC0 QC1
DIV_SELC Internal Pulldown MR/nOE Internal Pulldown
POWER-ON RESET 0 1
DIV_SELD Internal Pulldown
QD0 QD1 QD2 QD3 QD4
87951AYI
www.icst.com/products/hiperclocks.html
2
REV. A APRIL 15, 2002
Integrated Circuit Systems, Inc.
ICS87951I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
Type Power Input Input Input Input Input Power Input Input Input Power Output Output Output Output Input Input Input Pullup Pullup Pulldown Pulldown Pulldown Pulldown Description Analog supply pin. Feedback input to phase detector for regenerating clocks with "zero delay". LVCMOS / LVTTL interface levels. Selects divide value for Bank A output as described in Table 3D. LVCMOS / LVTTL interface levels. Selects divide value for Bank B output as described in Table 3D. LVCMOS / LVTTL interface levels. Selects divide value for Bank C outputs as described in Table 3D. LVCMOS / LVTTL interface levels. Selects divide value for Bank D outputs as described in Table 3D. LVCMOS / LVTTL interface levels. Power supply ground. Non-inver ting differential clock input.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7, 13, 17, 21, 25, 29 8 9 10 11, 15, 19, 23, 27 12, 14, 16, 18, 20 22, 24 26 28 30 31 32 Name VDDA EXT_FB DIV_SELA DIV_SELB DIV_SELC DIV_SELD GND CLK1 nCLK1 MR/nOE VDDO QD4, QD3, QD2, QD1, QD0 QC1, QC0 QB QA CLK0 PLL_SEL CLK_SEL
Pulldown Inver ting differential clock input. Master reset and output enable. When LOW, outputs are enabled. Pulldown When HIGH, outputs are disabled and dividers are reset. LVCMOS / LVTTL interface levels. Output supply pins. Bank D clock outputs. 7 typical output impedance. LVCMOS interface levels. Bank C clock outputs. 7 typical output impedance. LVCMOS interface levels. Bank B clock output. 7 typical output impedance. LVCMOS interface levels. Bank A clock output. 7 typical output impedance. LVCMOS interface levels. Pulldown LVCMOS / LVTTL phase detector reference clock input. Selects between the PLL and the reference clock as the input to the Pulldown dividers. When HIGH, selects PLL. When LOW, selects the reference clock. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK0. When LOW, Pulldown selects CLK1, nCLK1. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor VDDA, VDDO = 3.47V 25 51 51 Test Conditions Minimum Typical Maximum Units 4 pF pF K K
87951AYI
www.icst.com/products/hiperclocks.html
3
REV. A APRIL 15, 2002
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