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Details, datasheet, quote on part number:ICS87951I-147
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Integrated Circuit Systems, Inc.
HiPerClockSTM Application Note
High Speed LVCMOS Driver Termination Design Guide
This application note provides general design guide for high speed LVCMOS driver termination. To handle high speed LVCMOS drivers, general rules for high-speed digital board design must be carefully followed. Improper handling of the termination will cause signal reflection, clock ringing and lead to system failure. Proper termination is required to ensure signal integrity and Electro-Magnetic Interference (EMI) reduction. There are many different termination schemes for single ended LVCMOS drivers. This application note discusses parallel termination, AC termination and series termination. The following termination approaches are only general recommendations under ideal conditions. Board designers should consult with their signal integrity engineers and verify through simulations in their system environment.
Parallel Termination
The standard termination of an LVCMOS driver in a ZO=50 ohm transmission line environment is shown in Figure 1. The driver is terminated with 50 Ohm pull down to VTT=VDDO/2 at the receiver end. The LVCMOS clock buffer characterization set up is terminated in similar manner using split power supplies approach (See test condition in data sheet of an LVCMOS driver). In actual applications, the equivalent parallel termination shown in Figure 2 can be used. The LVCMOS parallel termination has the same effect as the standard LVCMOS shown in Figure 1. The parallel termination shown in Figure 2 can eliminate the need of VTT=VDDO/2 power supply (or reference voltage). The power dissipation calculation is described in a separate application note.
VDDO Zo = 50 Ohm Td
Ro ~ 7 Ohm
Driver_LVCMOS
R1 50 VDDO/2
Receiver
Figure 1 LVCMOS Driver Standard Termination
VDDO VDDO Zo = 50 Ohm Td R1 100
Ro ~ 7 Ohm
Driver_LVCMOS
R2 100
Receiver
Figure 2 LVCMOS Parallel Termination
www.icst.com/products/hiperclocks.html 1
Feb 27 2003
Integrated Circuit Systems, Inc.
HiPerClockSTM Application Note
High Speed LVCMOS Driver Termination Design Guide
AC Termination
The LVCMOS driver AC termination in a 50-ohm transmission line environment is shown in Figure 3. The majority of load current is drawn during transient region (i.e. rising edge and falling edge). This termination consumes less power than the parallel termination. The proper value of capacitor C1 depends on the trace delay and capacitance of the transmission line. Some software tools such as Hyperlynx provides a feature of calculating the transmission line capacitance by entering the trace information [1].
Ro ~ 7 Ohm
Zo = 50 Ohm
LVCMOS_Driver
R1 Zo=50
Receiver
C1
Figure 3 AC Termination
Series Termination
Series termination is a popular termination scheme for LVCMOS drivers. Figure 4 shows a simple series termination for LVCMOS drivers with output impedance of 7 Ohm. The Power Dissipation of this termination scheme is described in a separate document.
TM The typical output impedance RO of a HiPerClockS LVCMOS driver is approximately 7 ohms. (Some parts might have different Ro value. Refer to data sheet for the output impedance). The closest series resistor value, RS, can be calculated as follows
RS = ZO RO = 43 ohms In the Figure 4, the footprint for optional series resistor R3 or optional capacitor C1 at the receiver input is recommend for adjusting edge rate or overshoot if necessary.
www.icst.com/products/hiperclocks.html 2
Feb 27 2003
Integrated Circuit Systems, Inc.
HiPerClockSTM Application Note
High Speed LVCMOS Driver Termination Design Guide
Ro ~ 7 Ohm
Zo = 50 Ohm RS 43 R3 0 C1 SPARE Receiver
LVCMOS Driver
Figure 4 One to One LVCMOS Series Termination When the number of drivers is not equal to number of receivers as shown in Figure 6, the series resistor value RS is calculated as follows: RS = ZO (RO x M)/(N) Number of driver = N Number of receiver = M This configuration assumes that all the trace delays and load conditions are equally matched. For example, one driver driving 2 receivers as shown in Figure 5, with N=1and M=2, the series resistor is calculated to be RS = 36 Ohms. The trace delays Td on TL1 are equal. The loading conditions on both receivers should also be equal.
QA0 Ro ~ 7 Ohm RS1
Zo = 50 Ohm Td
8701
36 Ohm
TL1
Receiver
RS2
Zo = 50 Ohm Td
36 Ohm
TL2
Receiver
Figure 5 Series Termination for one LVCMOS Driver Driving Two Receiver
For 5 drivers driving 6 receivers, the closest series resistor can be calculated as follows: N=5, N=6, ZO=50 Ohms, RO =7 Ohm
www.icst.com/products/hiperclocks.html 3
Feb 27 2003
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