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Details, datasheet, quote on part number:ICS87952I
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS87952I
LOW SKEW, 1-TO-11 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
FEATURES
· Fully integrated PLL · 11 LVCMOS / LVTTL outputs, 7 typical output impedance · LVCMOS / LVTTL REF_CLK input · Output frequency range up to 180MHz at VDD = 3.3V ± 5% · VCO range: 240MHz to 480MHz · External feedback for "zero delay" clock regeneration · Cycle-to-cycle jitter: 100ps (typical) · 3.3V supply voltage · -40°C to 85°C ambient operating temperature · Compatible with MPC952
GENERAL DESCRIPTION
The ICS87952I is a low voltage, low skew LVCMOS/ LVTTL Clock Generator and a member of the H iPer Cl ockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. With output frequencies up to 180MHz, the ICS87952I is targeted for high performance clock applications. Along with a fully integrated PLL, the ICS87952I contains frequency configurable outputs and an external feedback input for regenerating clocks with "zero delay".
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For test and system debug purposes, the nPLL_EN input allows the PLL to be bypassed. When HIGH, the MR/nOE input resets the internal dividers and forces the outputs to the high impedance state. The low impedance LVCMOS/LVTTL outputs of the ICS87952I are designed to drive terminated transmission lines. The effective fanout of each output can be doubled by utilizing the ability of each output to drive two series terminated transmission lines.
BLOCK DIAGRAM
nPLL_EN
PIN ASSIGNMENT
GNDO GNDO VDDO VDDO QB1 QB0 QA4 QA3
REF_CLK
PHASE DETECTOR VCO 240-480MHz
1 0 ÷2
0 ÷4/÷6 1
24 23 22 21 20 19 18 17 QA0 QA1 QA2 VD D O QB2 QB3 GNDO GNDO QC0 QC1
÷4/÷2
25 26 27 28 29 30 31 32 1
VCO_SEL
16 15 14
VD D O QA2 QA1 GNDO QA0 VD D VDDA nPLL_EN
FB_IN
LFP
QA3 QA4
ICS87952I
13 12 11 10 9
VCO_SEL F_SELA
QB0 QB1
VD D O
2
F_SELC
3
F_SELB
4
F_SELA
5
MR/nOE
6
REF_CLK
7
GNDI
8
FB_IN
REV. A APRIL 30, 2003
F_SELB
QB2 QB3
÷2/÷4
QC0 QC1
F_SELC MR/nOE
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View
87952AYI
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1
Integrated Circuit Systems, Inc.
ICS87952I
LOW SKEW, 1-TO-11 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Type Input Input Input Input Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 Name VCO_SEL F_SELC F_SELB F_SELA Pulldown VCO select input. LVCMOS / LVTTL interface levels. Determines output divider values for Bank C as described in Table 3A. Pulldown LVCMOS / LVTTL interface levels. Determines output divider values for Bank B as described in Table 3A. Pulldown LVCMOS / LVTTL interface levels. Determines output divider values for Bank A as described in Table 3A. Pulldown LVCMOS / LVTTL interface levels. Active High Master Reset. Active LOW output enable. When logic LOW, the internal dividers and the outputs drivers are enabled. Pulldown When logic HIGH, the internal dividers are reset and the outputs are tri-stated (HiZ). LVCMOS / LVTTL interface levels. Pulldown Clock input. LVCMOS / LVTTL interface levels. Internal power supply ground. Feedback input to phase detector for generating clocks with Pulldown "zero delay". LVCMOS / LVTTL interface levels. PLL select input. Selects between REF_CLK and the PLL. Pulldown When HIGH, selects REF_CLK. When LOW, selects PLL. LVCMOS / LVTTL interface levels. Analog supply pin. Core supply pin. Bank A clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. Output power supply ground. Output supply pins. Bank B clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. Bank C clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels.
5 6 7 8 9 10 11 12, 14, 15, 18, 19 13, 17, 24, 28, 29 16, 20, 21, 25, 32 22, 23, 26, 27 30, 31
MR/nOE REF_CLK GNDI FB_IN nPLL_EN VDDA VDD QA0, QA1, QA2, QA3, QA4 GNDO VDDO QB0, QB1, QB2, QB3 QC0, QC1
Input Input Power Input Input Power Power Output Power Power Output Output
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance Test Conditions Minimum Typical 4 51 VDD, VDDA, VDDO = 3.465V 25 7 Maximum Units pF K pF
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Input F_SELA 0 1
87952AYI
TABLE 3B. CONTROL SELECT FUNCTION TABLE
Input F_SELC 0 1 Output QC0:QC1 ÷2 ÷4 Control Input VCO_SEL MR/nOE nPLL_EN Logic 0 fVCO Output Enable Enable PLL Logic 1 fVCO/2 HiZ Disable PLL
REV. A APRIL 30, 2003
Output QA0:QA4 ÷4 ÷6
Input F_SELB 0 1
Output QB0:QB3 ÷4 ÷2
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2
Integrated Circuit Systems, Inc.
ICS87952I
LOW SKEW, 1-TO-11 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9°C/W (0 lfpm) -65°C to 150°C N O T E : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol VDD VDDA VDDO IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current 15 Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 160 20 Units V V V mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage REF_CLK, Input MR/nOE, FB_IN, VCO_SEL, High Current F_SELA:F_SELC, nPLL_EN REF_CLK, Input MR/nOE, FB_IN, VCO_SEL, Low Current F_SELA:F_SELC, nPLL_EN Output High Voltage Output Low Voltage Test Conditions Minimum Typical 2 -0.3 VDD = VIN = 3.465V Maximum VDD + 0.3 0.8 120 Units V V µA
IIL VOH VOL
VDD = 3.465V, VIN = 0V IOH = -20mA IOL = 20mA
-120 2.4 0.5
µA V V
TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Input Reference Frequency NOTE: Input reference frequency is limited by fREF the divider selection and the VCO lock range. Test Conditions Minimum Typical Maximum 100 Units MHz
87952AYI
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3
REV. A APRIL 30, 2003
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