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Details, datasheet, quote on part number:ICS87973CYI
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| Part: | ICS87973CYI |
| Category: | Timing Circuits => Clock Buffers => Zero Delay Fanout |
| Description: | Lowskew 1-to-12 Lvcmos Multiplier/ Zero Delay Buffer. Pin Compatiblewith MPC973. Industrial Temperature. |
| Company: | Integrated Circuit System |
| Datasheet: | Download ICS87973CYI datasheet File size : 183 kB |
| Request For quote: | Find where to buy ICS87973CYI
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS87973I
LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
FEATURES
· Fully integrated PLL · 14 LVCMOS/LVTTL outputs; (12) clock, (1) feedback, (1) sync · Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs · CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL · CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL · Output frequency range: 8.33MHz to 125MHz · VCO range: 200MHz to 480MHz · Output skew: 550ps (maximum) · Cycle-to-cycle jitter: ±100ps (typical) · Full 3.3V supply voltage · -40°C to 85°C ambient operating temperature · Pin compatible with MPC973 · Compatible with PowerPCTM and PentiumTM Microprocessors
GENERAL DESCRIPTION
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H iPer Cl ockSTM
The ICS87973I is a LVCMOS/LVTTL clock generator and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS87973I has three selectable inputs and provides 14 LVCMOS/LVTTL outputs.
The ICS87973I is a highly flexible device. The three selectable inputs (1 differential and 2 single ended inputs) are often used in systems requiring redundant clock sources. Up to three different output frequencies can be generated among the three output banks. The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output frequency range is 8.33MHz to125MHz. The input frequency range is 5MHz to 120MHz. The ICS87973I also has a QSYNC output which can by used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another. Example Applications: 1. System Clock generator: Use a 16.66MHz reference clock to generate eight 33.33MHz copies for PCI and four 100MHz copies for the CPU or PCI-X. 2. Line Card Multiplier: Multiply differential 62.5MHz from a back plane to single-ended 125MHz for the line Card ASICs and Gigabit Ethernet Serdes. 3. Zero Delay buffer for Synchronous memory: Fan out up to twelve 100MHz copies from a memory controller reference clock to the memory chips on a memory module with zero delay.
PIN ASSIGNMENT
EXT_FB GNDO GNDO GNDO VD D O VD D O QB0 QB1 QB2 QB3 QFB VDD
FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 VDDO QA2 GNDO QA1 VDDO QA0 GNDO VC O _ S E L
39 38 37 36 35 34 33 32 31 30 29 28 27 40 26 41 42 43 44 45 46 47 48 49 50 51 52 1 GNDI 2 nMR/OE 3 FRZ_CLK 4 FRZ_DATA 56 FSEL_FB2 PLL_SEL 78 REF_SEL CLK_SEL 9 10 11 12 13 CLK0 CLK1 CLK nCLK VDDA 25 24 23 22 21
FSEL_FB0 FSEL_FB1 QSYNC GNDO QC0 VD D O QC1 FSEL_C0 FSEL_C1 QC2 VD D O QC3 GNDO INV_CLK
ICS87973I
20 19 18 17 16 15 14
52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View
87973DYI
www.icst.com/products/hiperclocks.html
1
REV. D JUNE 27, 2003
Integrated Circuit Systems, Inc.
ICS87973I
LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
BLOCK DIAGRAM
VCO_SEL PLL_SEL REF_SEL CLK nCLK CLK0 CLK1 CLK_ SEL EXT_FB 0 1 PHASE DETECTOR LPF VCO 1 0 0 1
D Q
SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ
QA0 QA1 QA2 QA3
D
Q
SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ
QB0 QB1 QB2 QB3
FSEL_FB2
nMR/OE POWER-ON RESET ÷4, ÷6, ÷8, ÷12 ÷4, ÷6, ÷8, ÷10 ÷2, ÷4, ÷6, ÷8 2 2 F S E L _ B 0 :1 FSEL_C0:1 FSEL_FB0:2 2 3 DATA GENERATOR SYNC PULSE 0 ÷2 1
D
Q
SYNC FRZ
QC0 QC1 QC2 QC3 QFB
D
Q
SYNC FRZ SYNC FRZ
F S E L _A 0 : 1
÷4, ÷6, ÷8, ÷10
D
Q
D
Q
S Y NC FRZ
QSYNC
FRZ_CLK OUTPUT DISABLE C I R C U I T RY 12
FRZ_DATA
INV_CLK
87973DYI
www.icst.com/products/hiperclocks.html
2
REV. D JUNE 27, 2003
Integrated Circuit Systems, Inc.
ICS87973I
LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
nMR/OE
SIMPLIFIED BLOCK DIAGRAM
FSEL_A[0:1]
CLK nCLK CLK0 CLK1 CLK_ SEL REF_SEL
÷2 1 0 1 VCO RANGE 200MHz - 480MHz 0 0 1 ÷1 1 0 PLL
2
FSEL_ A1 A0 00 01 10 11
QAx ÷4 ÷6 ÷8 ÷12
SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ
QA0 QA1 QA2 QA3
EXT_FB
FSEL_B[0:1]
2
VCO_SEL
PLL_SEL
FSEL_ B1 B0 00 01 10 11
QBx ÷4 ÷6 ÷8 ÷10
SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ
QB0 QB1 QB2 QB3
FSEL_C[0:1]
2
FSEL_ C1 C0 00 01 10 11
QCx ÷2 ÷4 ÷6 ÷8
QC0
SYNC FRZ
QC1 QC2 QC3
0
SYNC FRZ SYNC FRZ
1 INV_CLK FSEL_FB[0:2]
3
FSEL_ FB2 FB1 FB0 QFB 0 0 0 ÷4 0 0 1 ÷6 0 1 0 ÷8 0 1 1 ÷10 1 0 0 ÷8 1 0 1 ÷12 1 1 0 ÷16 1 1 1 ÷20
FRZ_CLK FRZ_DATA
OUTPUT DISABLE CIRCUITRY SYNC FRZ
QFB
QSYNC
87973DYI
www.icst.com/products/hiperclocks.html
3
REV. D JUNE 27, 2003
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