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Details, datasheet, quote on part number:ICS87974
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Datasheet text preview:
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS87974I-01
LOW SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS / LVTTL CLOCK GENERATOR
FEATURES
· Fully integrated PLL · 15 single ended 3.3V LVCMOS / LVTTL outputs · Selectable LVCMOS_CLK or differential CLK0, nCLK0 inputs for redundant clock applications · LVCMOS_CLK accepts LVCMOS or LVTTL input levels · CLK0, nCLK0 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL · Maximum output frequency: TBD · External feedback for "zero delay" clock regeneration · Cycle-to-cycle jitter: 50ps (maximum) · Output skew: 200ps (maximum) · Bank skew: TBD · PLL reference zero delay: TBD · 3.3V operating supply · -40°C to 85°C ambient operating temperature
GENERAL DESCRIPTION
The ICS87974I-01 is a low skew, low jitter 1-to-15 Differential-to-LVCMOS / LVTTL Clock Generator/ H iPerC lockSTM Z e r o Delay Buffer and is a member of the HiPerClockS family of High Performance Clock Solutions from ICS. The device has a fully integrated PLL and three banks whose divider ratios can be independently controlled, providing output frequency relationships of 1:1, 2:1, 3:1, 3:2, 3:2:1. In addition, the external feedback connection provides for a wide selection of output-toinput frequency ratios. The LVCMOS_CLK and CLK0, nCLK0 pins allow for redundant clocking on the input and dynamically switching the PLL between two clock sources.
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Guaranteed low jitter and output skew characteristics make the ICS87974I-01 ideal for those applications demanding well defined performance and repeatability.
PIN ASSIGNMENT
VCO_SEL V DDOC V DDOC VDDOB GND GND GND QC3 QC0 QC1 QC2 QB0 nc
GND nMR CLK_EN SEL_B SEL_C PLL_SEL SEL_A CLK_SEL LV C M O S _ C L K CLK0 nCLK0 VDD VDDA
1 2 3 4 5 6 7 8 9
5 2 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
GND QB1 VDDOB QB2 GND QB3 VDDOB QB4 FB_IN GND QFB VDDOFB nc
ICS87974I-01
33 32 31 30 29 28
10 11 12
13 27 1 4 15 16 17 18 19 20 21 22 23 24 25 26
QA4 QA3 QA2 QA1 VDDOA VDDOA QA0 FB_SEL0 FB_SEL1 VDDOA GND GND GND
52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87974AYI-01
www.icst.com/products/hiperclocks.html
1
REV. A MAY 15, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS87974I-01
LOW SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS / LVTTL CLOCK GENERATOR
BLOCK DIAGRAM
SEL_A CLK_SEL
(Internal Pulldown) (Internal Pulldown)
LVCMOS_CLK (Internal Pulldown)
÷2 PLL 0 1 ÷4 0 1
0 C L K 0 (Internal Pulldown) 1 n C L K 0 (Internal Pullup)
FB_IN (Internal Pullup)
÷2 ÷4 ÷6
0
DQ 5 QA0:QA4
1
P L L _ S E L (Internal Pullup) V C O _ S E L (Internal Pulldown) S E L _ B (Internal Pulldown)
0
DQ 5 QB0:QB4
1
0
DQ 4 QC0:QC3
1
S E L _ C (Internal Pulldown)
n M R (Internal Pullup) FB_SEL0 FB_SEL1
(Internal Pulldown)
0 1 ÷2
0
DQ QFB
1
(Internal Pulldown)
C L K _ E N (Internal Pullup)
87974AYI-01
www.icst.com/products/hiperclocks.html
2
REV. A MAY 15, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS87974I-01
LOW SKEW, 1-TO-15, DIFFERENTIAL-TO-LVCMOS / LVTTL CLOCK GENERATOR
Type Power Description Power supply ground. Active LOW Master Reset. When logic LOW, the internal dividers are reset causing the outputs to go low. when logic HIGH, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Clock enable. When LOW, all outputs except QFB are low. LVCMOS / LVTTL interface levels. Selects divide value for Bank B output as described in Table 3. LVCMOS / LVTTL interface levels. Selects divide value for Bank C output as described in Table 3. LVCMOS / LVTTL interface levels. Selects between the PLL and the reference clock as the input to the dividers. When HIGH, selects PLL. When LOW, selects the reference clock. LVCMOS / LVTTL interface levels. Selects divide value for Bank A output as described in Table 3. LVCMOS / LVTTL interface levels. Clock select input. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 15, 19, 24, 30, 35, 39, 43, 47, 51 2 Name GND
nMR
Input
Pullup
3 4 5 6 7 8 9 10 11 27, 42 12 13 14, 20 16, 18, 21, 23, 25 17, 22, 26 28 29 31
CLK_EN SEL_B SEL_C PLL_SEL SEL_A CLK_SEL LVCMOS_CLK CLK0 nCLK0 nc VDD VDDA FB_SEL0, FB_SEL1 QA4, QA3, QA2, QA1, QA0 VDDOA VDDOFB QFB FB_IN
Input Input Input Input Input Input Input Input Input Unused Power Power Input Output Power Power Output Input Output Power Output Power Input
Pullup Pulldown Pulldown Pullup Pulldown Pulldown
Pulldown Clock input. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input No connect. Core supply pin. Analog supply pin. Selects divide value for Bank feedback output as described in Pulldown Table 3. LVCMOS / LVTTL interface levels. Bank A clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. Output supply pins for Bank A clock outputs. Output supply pin for QFB clock output. Clock output. LVCMOS / LVTTL interface levels. Feedback input to phase detector for generating clocks with Pullup "zero delay". Connect to pin 29. LVCMOS / LVTTL interface levels. Bank B clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. Output supply pins for Bank B clock outputs. Bank C clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. Output supply pins for Bank C clock outputs. Selects VCO ÷ 4 when HIGH. Selects VCO ÷ 2 when LOW. Pulldown LVCMOS / LVTTL interface levels.
32, 34, QB4, QB3, 36, 38, 40 QB2, QB1, QB0 33, 37, 41 VDDOB 44, 46, QC3, QC2, 48, 50 QC1, QC0 45, 49 VDDOC 52 VCO_SEL
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87974AYI-01
www.icst.com/products/hiperclocks.html
3
REV. A MAY 15, 2003
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