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Details, datasheet, quote on part number:ICS87974AYI
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| Part: | ICS87974AYI |
| Category: | Timing Circuits => Clock Buffers => Zero Delay Fanout |
| Description: | Lowskew 1-to-15 Lvcmos Clock Generator. Pin Compatible With MPC974.Industrial Temperature. |
| Company: | Integrated Circuit System |
| Datasheet: | Download ICS87974AYI datasheet File size : 174 kB |
| Request For quote: | Find where to buy ICS87974AYI
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS87974I
LOW SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR
FEATURES
· Fully integrated PLL · 15 single ended 3.3V LVCMOS/LVTTL outputs · 2 LVCMOS/LVTTL clock inputs for redundant clock applications · CLK0 and CLK1 accepts the following input levels: LVCMOS/LVTTL · Output frequency range: 8.33MHz to 125MHz · VCO range: 200MHz to 500MHz · External feedback for "zero delay" clock regeneration · Cycle-to-cycle jitter: ±100ps (typical) · Output skew: 350ps (maximum) · 3.3V operating supply · -40°C to 85°C ambient operating temperature · Pin compatible with the MPC974
GENERAL DESCRIPTION
The ICS87974I is a low skew, low jitter 1-to-15 LVCMOS/LVTTL Clock Generator/Zero Delay H iPerC lockSTM Buffer and is a member of the HiPerClockS family of high performance clock solutions from ICS. The device has a fully integrated PLL and three banks whose divider ratios can be independently controlled, providing output frequency relationships of 1:1, 2:1, 3:1, 3:2, 3:2:1. In addition, the external feedback connection provides for a wide selection of output-to-input frequency ratios. The CLK0 and CLK1 pins allow for redundant clocking on the input and dynamically switching the PLL between two clock sources. The ICS87974I is pin for pin compatible with the MPC974.
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Guaranteed low jitter and output skew characteristics make the ICS87974I ideal for those applications demanding well defined performance and repeatability.
PIN ASSIGNMENT
VCO_SEL V DDOC V DDOC VDDOB GND GND GND QC3 QC0 QC1 QC2 QB0 nc
GND nMR/OE CLK_EN SEL_B SEL_C PLL_SEL SEL_A CLK_SEL CLK0 CLK1 nc VDD VDDA
1 2 3 4 5 6 7 8 9
5 2 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
GND QB1 VDDOB QB2 GND QB3 VDDOB QB4 FB_IN GND QFB VDDOFB nc
ICS87974I
33 32 31 30 29 28
10 11 12
13 27 1 4 15 16 17 18 19 20 21 22 23 24 25 26
FB_SEL0 GND QA4 VDDOA QA3 GND FB_SEL1 QA2 VDDOA QA1 GND QA0 VDDOA
52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View
87974AYI
www.icst.com/products/hiperclocks.html
1
REV. B MAY 15, 2003
Integrated Circuit Systems, Inc.
ICS87974I
LOW SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR
BLOCK DIAGRAM
SELA CLK_SEL
(Internal Pulldown) (Internal Pulldown)
C L K 0 (Internal Pulldown) 0 C L K 1 (Internal Pullup) FB_IN (Internal Pullup) P L L _ S E L (Internal Pullup) VCO_SEL
(Internal Pulldown)
0
PLL
÷2 ÷4
0
0 1
÷2 ÷4 ÷6
DQ
5
QA0:QA4
1
1
1
0
DQ 5 QB0:QB4
1
SELB (Internal Pulldown)
0
DQ 4 QC0:QC3
1
S E L C (Internal Pulldown)
0
nMR/OE (Internal Pullup)
0
DQ QFB
1
FB_SEL0
(Internal Pulldown)
÷2
1
FB_SEL1 (Internal Pulldown)
C L K _ E N (Internal Pullup)
87974AYI
www.icst.com/products/hiperclocks.html
2
REV. B MAY 15, 2003
Integrated Circuit Systems, Inc.
ICS87974I
LOW SKEW, 1-TO-15, LVCMOS/LVTTL CLOCK GENERATOR
SIMPLIFIED BLOCK DIAGRAM
CLK_EN SEL_A VCO_SEL
CLK_SEL CLK0 CLK1 FB_IN PLL_SEL SEL_B
0 0 1 PLL 1
÷2
0
÷4
1
SEL_A 0 ÷2 1 ÷4
DQ
5
QA0:QA4
SEL_B 0 ÷2 1 ÷4
DQ
5
QB0:QB4
SEL_C 0 ÷4 1 ÷6
SEL_C
DQ
4
QC0:QC3
FB_1 FB_0 0 0 ÷4 0 1 ÷6 1 0 ÷8 1 1 ÷12
DQ
QFB
FB_SEL(0:1) nMR/OE
2
87974AYI
www.icst.com/products/hiperclocks.html
3
REV. B MAY 15, 2003
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