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Details, datasheet, quote on part number:ICS9147-09
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| Part: | ICS9147-09 |
| Category: | Timing Circuits => Clock Generators => Motherboard |
| Description: | Frequency Generator & Integrated Buffers For 686 Series Cpus |
| Company: | Integrated Circuit System |
| Datasheet: | Download ICS9147-09 datasheet File size : 616 kB |
| Request For quote: | Find where to buy ICS9147-09
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS9147-09
Frequency Generator & Integrated Buffers for 686 Series CPUs
General Description
The ICS9147-09 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro,AMD or Cyrix processors. Four bidirectional I/O pins (FS0, FS1, FS2, BSEL) are latched at power-on to the functionality table. The Six BUS clocks can be selected as either synchronous at 1/2 CPU speed or asynchronous at 32MHz selected by BSEL latched input.The inputs provide for tristate and test mode conditions to aid in system level testing.These multiplying factors can be customized for s p e c i f i c applications. Glitch-free stop clock controls provided for CPU. High drive BUS and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30 pF loads. CPU outputs typically provide better than 1V/ns slew rate into 20pF loads while maintaining 50±5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. Seperate buffer supply pin VDDL allows for nominal 3.3V voltage or reduced voltage swing (from 2.9 to 2.5V) for CPUL (1:2) and IOAPIC outputs.
Features
Total of 15 CPU speed clocks: - Two copies of CPU clock with VDDL (2.5 to 3.3V) - Twelve (12) SDRAM (3.3v) plus one CPUH/AGP (3.3V) clocks Six copies of BUS clock (synchronous with CPU clock/2 or asynchronous 32 MHz) 250ps output skew window for CPU andSDRAM clocks and 500ps window BUS clocks. CPU clocks to BUSclocks skew 1-4ns (CPU early) Two copies of Ref. clock @14.31818 MHz (One driven by VDDL as IOAPIC) One 48 MHz (3.3 V TTL) for USB support and single 24 MHz. Separate VDDL for CPUL (1:2) clock buffers and IOAPIC to allow 2.5V output (or Std. Vdd) 3.0V 3.7V supply range w/2.5V compatible outputs 48-pin SSOP package
Block Diagram
Pin Configuration
48-Pin SSOP
Pentium is a trademark of Intel Corporation 9147-09 Rev A 10/2897P
I C S reserves the right to make changes in the device data identified in this p u b l i c a t i o n without further notice. ICS advises its customers to obtain the latest v e r s i o n of all device data to verify that any information being relied upon by the c u s t o m e r is current and accurate.
ICS9147-09
Pin Descriptions
P I N NUMBER REF 2 FS1 3, 9, 16, 22, 27, 33, 39, 45 4 5 41 8, 10, 11, 12, 14, 15 FS0 23 24 47 BS EL 1, 6, 13, 19, 30, 36, 48 17, 18, 20, 21, 28, 29, 31, 32, 34, 35, 37, 38 40 42, 43 7, 25, 26 46 FS2 44 IO A PIC IN OUT Logic input frequency select Bit 2*. Input latched at Poweron. Reference clock (14.318MHz) powered by VDDL, o perating 2.5 to 3.3V. V DD 3 SDRAM (1:12) CP U H/ A GP CPUL (1:2) N/ C 48M IN PWR OUT OUT OUT -- OUT C P U _ S TO P # PD # 24M IN IN IN OUT Logic input frequency select Bit0.*. Input latched at Poweron. Halts CPU Clocks at Logic "0" level when low. Internal Pull-up Powers down chip, active low. Internal Pull-up 2 4MHz fixed clock.* Logic input* for selecting synchronous or asynchronous BUS frequency- see table above. Input latched at Poweron.* 3 .3 volt core logic and buffer power SDRAM clocks at CPU speed. See select table for frequency. CPU clock operates at SDRAM VDD level (3.3V nom), for AGP etc. CPU clocks .See select table for frequency. Operates at down to 2 .5V controlled by VDDL pin. Pins not internally connected. 4 8 MHz fixed clock output*. G ND X1 X2 V DD L BUS (1:5) BUS6 IN PWR IN OUT PWR OUT OUT Logic input frequency select Bit1*. Input latched at Poweron. Ground. Crystal input. Nominally 14.318 MHz. Has internal load cap Crystal output. Has internal load cap and feedack resistor to X1 2 .5 or 3.3V buffer power for CPUL and IOAPIC output buffers. BUS clock outputs. see select table for frequency BUS clock output. See select table for frequency.* P I N NAME TYPE OUT Reference clock output* D ESC RIPTI ON
* Bidirectional input/output pins, input logic level determined at internal power-on-reset are latched. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
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ICS9147-09
Functionality with (14.31818 MHz input)
Address Select CPUL (1:2) CPUH SDRAM (1:12) (MHz) 60 66.8 50 55 75 68.5 83.3 Tristate BUS (1:6) (MHz) BSEL=1 BSEL=0 30 33.4 25 27.5 37.5 34.3 41.65 Tristate 32 32 32 32 32 32 32 Tristate 24M (MHz) (MHz) 24 24 24 24 24 24 24 Tristate 48M (MHz) (MHz) 48 48 48 48 48 48 48 Tristate
FS2 0 0 0 0 1 1 1 1
FS1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1
* * Test: is the frequency applied to the X1 input. Can be crystal or tester generated clock overriding crystal at X1 pin.
Clock Enable Configuration
PD# 1 1 0 CPUSTOP# 1 0 X CPUL (1:2) CPUH Running Stop Low Stop Low SDRAM BUS (1:6) (1:12) Running Running Running Running 24MHz 48MHz REF Running Running Running Running Running Running
Stop Low Stop Low Stop Low Stop Low Stop Low
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