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Details, datasheet, quote on part number:ICS9147-16
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS9147-16
Frequency Generator & Integrated Buffers for PENTIUMTM
General Description
The ICS9147-16 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro. Two different reference frequency multiplying factors are externally selectable with smooth frequency transitions. Glitch-free Stop clock control is provided for CPU and BUS clocks. Complete chip low current mode is achieved with the Power Down# pin. High drive BUS outputs typically provide greater than 1 V/ ns slew rate into 30 pF loads. CPU outputs typically provide b e t t e r than 1V/ns slew rate into 20 p F loads while maintaining 50± 5% duty cycle. The REF and IOAPIC clock outputs typically provide better than 0.5V/ns slew rates. Separate buffer supply pins VDDL allow for nominal 3.3V voltage or reduced voltage swing (from 2.9 to 2.5V) for CPU (1:4) and IOAPIC outputs.
Features
Generates four processor, eight bus, four 14.31818 MHz, two 48 MHz clocks for USB support. CPU to BUS clock skew 1 to 4ns (CPU early) Synchronous clocks skew matched to 250ps window on CPU and 500ps window on BUS. Selectable multiplying ratios Glitch free stop clock controls CPUEN and BUSEN 3.0V 3.7V supply range, 2.5V to VDD supply range for CPU (1:4) clocks and IOAPIC clock. 48-pin SSOP package
Pin Configuration
Block Diagram
48-Pin SSOP
Pentium is a trademark of Intel Corporation 9147-16 Rev A 072897P
I C S reserves the right to make changes in the device data identified in this p u b l i c a t i o n without further notice. ICS advises its customers to obtain the latest v e r s i o n of all device data to verify that any information being relied upon by the c u s t o m e r is current and accurate.
ICS9147-16
Functionality
PD# 1 1 1 1 1 1 0 BUSEN 1 1 1 1 1 0 X CPUEN 1 1 1 1 0 1 X FS1 0 0 1 1 X X X FS0 0 1 0 1 X X X CPU (1:4) Tristate 60 66.6 REF/2 LOW Running LOW BUS Tristate 30 33.3 REF/4 Running LOW LOW REF IOAPIC Tristate 14.31818 14.31818 REF 14.31818 14.31818 LOW 48 (MHz) Tristate 48 48 REF/2 48 48 LOW
Pin Descriptions
P I N NUMBER P I N NAME 1, 2, 47 REF1, REF2, REF3 3, 10, 18, 24, 30, 32, GND 37, 43, 44 4 5 8, 9, 11, 12, 13, 14, 16, 17 26, 27 7, 15, 21, 25, 34, 48 22, 23 28 29 38, 39, 41, 42 6 45 40, 46 19, 20, 31, 33, 36 X1 X2 BUS (1:8) FS (0:1) VDD3 48M (1:2) P D# C P UE N CPU (1:4) B US E N I OA P I C V DD L N/C TYP E OUT P WR IN OUT OUT IN P WR OUT IN IN OUT IN OUT P WR DE SC RI P TI ON 14.318 MHz reference clock outputs. Gro u n d . Crystal input, has internal crystal load capacitor, and feedback resistor from X2. Nominally 14.31818MHz. Crystal output, has internal crystal load capacitor BUS clock outputs, operates synchronously at CPU/2. Select pin for enabling CPU and BUS clock frequencies.* Core and Buffer output clock power supply. 48 MHz clock output Device power down input, stops outputs low and shuts off crystal oscillator and PLLs when low.* Output enable for all CPU clocks, a logic low will Stop low all CPU c lo c k s . * CPU clock output clocks, operates at VDDL supply voltage (with IOAPIC), either nominal 3.3V VDD or reduced voltage 2.9 to 2.5V. Output enable for all BUS clock, a logic low will stop Low all Bus c lo c k s . * IOAPIC clock output. (14.318 MHz), operates at VDDL supply voltage with CPU (1:4), either nominal 3.3V VDD or reduced voltage 2.9 to 2.5V. Power supply for CPU and IOAPIC block buffers, operates at nominal 3.3V VDD or reduced voltage 2.9 to 2.5V. No connection internally to these pins.
* Has internal pull-up to VDD3.
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ICS9147-16
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V L o g i c Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 3.3V
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current SYMBOL VIL VIH IIL IIH IOL1
VDDL=VDD3=3.0 3.7 V, TA = 0 70° C unless otherwise stated
DC Characteristics
TEST CONDITIONS MIN 0.7VDD -28.0 -5.0 19.0 TYP -10.5 30.0 MAX 0.2VDD 5.0 UNITS V V µA µA mA
IOH1a Output High Current IOH1b Output Low Current Output High Current Output Low Current IOL2 IOH2 IOL3 IOH3a Output High Current IOH3b Output Low Voltage
VOL1
Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Supply Current Supply Current
VOH1 VOL2 VOH2 VOL3 VOH3 IDD IDDPD
VIN = 0V VIN = VDD VOL = 0.8V; for BUS & REF1 (and CPU & IOAPIC at VDDL= 3.0 to 3.7V) VOH = 2.0V; for BUS & REF1 (and IOAPIC at VDDL = 3.0 to 3.7V) VOH = 2.0V; for CPU @ VDDL = 3.0 to 3.7V VOL = 0.8V; REF (2:3), 48 CLKs VOH = 2.0V; REF (2:3), 48 CLKs VOL=0.8V; for CPU at VDDL = 2.5V VOH = 2.0V; for CPU at VDDL = 2.5V VOH = 2.0V; for IOAPIC @ VDDL = 2.5V IOL = 10mA; for BUS & REF1 (and CPU at VDDL = 3.0 to 3.7V) IOH = -10mA; for BUS & REF1 (and CPU at VDDL = 3.0 to 3.7V) IOL = 4mA; REF (2:3), 48 CLKs IOH = -4mA; REF (2:3), 48 CLKs IOL = 8mA; for CPU at VDDL = 2.5V IOH = -8mA; for CPU at VDDL = 2.5V @66.6 MHz; all outputs unloaded PD# = Low
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-28.0 -45.0
-16.0 -27.0 -7.0 -9.5 -10.0 0.4
mA mA mA mA mA mA mA V
8.0 19.0 -
13.0 -11.0 30.0 -12.5 -13.0
-
0.22
2.4 2.4 2.1 -
2.8 0.25 2.6 0.25 2.25 70 230
0.4 0.4 140 500
V V V V V mA µA
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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