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Details, datasheet, quote on part number:ICS9147-22
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS9147-22
Pentium/ProTM System and Cyrix Clock Chip
General Description
The ICS9147-22 is a Clock Synthesizer chip for Pentium and PentiumPro plus Cyrix CPU based Desktop/Notebook systems that will provide all necessary clock timing. Features include four CPU, seven PCI and eight SDRAM clocks. Two reference outputs are available equal to the crystal frequency, plus the IOAPIC output powered by VDDL. Additionally, the device meets the Pentium powerup stabilization, which requires that CPU and PCI clocks be stable within 2ms after power-up. High drive PCICLK and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30 pF loads. CPUCLK outputs typically provide better than 1V/ns slew rate into 20 pF loads while maintaining 50 ± 5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. The ICS9147-22 accepts a 14.318MHz reference crystal or clock as its input and runs on a 3.3V supply.
Features
Generates system clocks for CPU, IOAPIC, SDRAM, PCI, plus 14.318 MHz (REF0:1), USB, Super I/O Supports single or dual processor systems Supports Intel 60, 66.8MHz, Cyrix 55, 75MHz plus 83.3 and 68MHz (Turbo of 66.6) speeds. Synchronous clocks skew matched to 250ps window on CPU, SDRAM and 500ps window on PCI clocks CPU clocks to PCI clocks skew 1-4ns (CPU early) Two fixed outputs, 48MHz and 24 MHz Separate 2.5V and 3.3V supply pins - 2.5V or 3.3V output: CPU, IOAPIC - 3.3V outputs: SDRAM, PCI, REF, 48/24 MHz No power supply sequence requirements 48 pin 300 mil SSOP
Pin Configuration
Block Diagram
48-Pin SSOP Power Groups
VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK (0:5) VDD3 = SDRAM (0:7), VDD4 = 48MHz, 24MHz VDDL = IOAPIC, CPUCLK (0:3)
Pentium is a trademark on Intel Corporation. 9147-22 Rev A 072597P
I C S reserves the right to make changes in the device data identified in this p u b l i c a t i o n without further notice. ICS advises its customers to obtain the latest v e r s i o n of all device data to verify that any information being relied upon by the c u s t o m e r is current and accurate.
ICS9147-22
Pin Descriptions
PIN NUMBER 1 2 3, 10, 17, 24, 31, 31, 37, 43 4 5 6, 47 7, 15 8 9, 11, 12, 13, 14, 16 18 19 20 21 22 23 25, 28,34 26, 27, 29, 30, 32, 33, 35, 36 38, 39, 41, 42 40, 46 44 45 48 PIN NAME REF1 REF0 GND X1 X2 N/C VDD2 PCICLK_F PCICLK (0:5) FS0 FS1 FS2 VDD4 48MHz 24MHz VDD3 SDRAM (0:7) CPUCLK (0:3) VDDL PD# IOAPIC VDD1 TYPE OUT OUT PWR IN OUT PWR OUT OUT IN IN IN PWR OUT OUT PWR OUT OUT PWR IN OUT PWR DESCRIPTION Reference clock output Reference clock output Ground (common) Crystal or reference input, nominally 14.318 MHz. Includes internal load cap to GND and feedback resistor from X2. Crystal output, includes internal load cap to GND. Pins are not internally connected Supply for PCICLKF, and PCICLK (0:5) Free running PCI clock PCI clocks Frequency select 0 input1 Frequency select 1 input1 Frequency select 2 input1 Supply for 48MHz and 24MHz clocks 48MHz driver output for USB clock 24MHz driver output for Super I/O clock Supply for SDRAM (0:7) SDRAMs clock at CPU speed CPUCLK clock output, powered by VDDL Supply for CPUCLK (0:3) + IOAPIC Power down stops all clocks low and disables oscillator and internal VCO's.2 IOAPIC clock output, powered by VDDL at crystal frequency Supply for REF (0:1), X1, X2
Note 1: Internal pull-up resistor of nomimally 100K to 120K at 3.3V on indicated inputs. Note 2: The PD# input pin has a protection diode clamp to the VDDL power supply. If VDDL is not connected to VDD, (ie VDDL=2.5V, VDD=3.3V) then this input must have a series resistor if the logic high is connected to VDD. This input series resistor provides current limit for the clamp diode. For a pullup to VDD it should be 1Kohm or more from the PD# pin to VDD. If the PD# pin is being driven by logic powered by 3.3V, then a 100 series resistor will be suffcient.
2
ICS9147-22
Functionality
VDD = 3.3V ±5% VDDL = 2.5V ±5% or 3.3V ±5%, TA = 0 to 70° Crystal (X1, X2) = 14.31818 MHz
FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPUCLK, SDRAM (MHz) 8.33 75 83.3 68.5 55 75 60 66.8 PCICLK (MHz) 1/2 CPU 30 33.3 1/2 CPU 1/2 CPU 1/2 CPU 1/2 CPU 1/2 CPU
Power Management Functionality
PD# CPUCLK Outputs Stopped Low Running PCICLK(0:5) Outputs Stopped Low Running PCICLK_F, REF, 24/48MHz and SDRAM Stopped Low Running Crystal OSC Off Running VCO
0 1
Off Running
3
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