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Details, datasheet, quote on part number:ICS9148-08
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS9148-08
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9148-08 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Cyrix. Eight different reference frequency multiplying factors are externally selectable with smooth frequency transitions. Features include four CPU, seven PCI and Twelve SDRAM clocks. Two reference outputs are available equal to the crystal frequency. Plus the IOAPIC output powered by VDDL1. One 48 MHz for USB, and one 24 MHz clock for Super IO. Spread Spectrum built in ±1.5% modulation to reduce the EMI. Serial programming I2C interface allows changing functions, stop clock programing and Frequency selection. Rise time adjustment for VDD at 3.3V or 2.5V CPU. A d d i t i o n a l l y, the device meets the Pentium power-up stabilization, which requires that CPU and PCI clocks be stable within 2ms after power-up. It is not recommended to use I/O dual function pin for the slots (ISA, PCI, CPU, DIMM). The add on card might have a pull up or pull down. High drive PCICLK and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs typically provide better than 1V/ns slew rate into 20pF loads while maintaining 50±5% duty cycle. The REF and 24 and 48 MHz clock outputs typically provide better than 0.5V/ns slew rates.
Features
3.3V outputs: SDRAM, PCI, REF, 48/24 MHz 2.5V or 3.3V outputs; CPU, IOAPIC 20 ohm CPU clock output impedance 20 ohm PCI clock output impedance Skew from CPU (earlier) to PCI clock - 1 to 4 ns, center 2.6 ns. No external load cap for CL=18pF crystals ±250 ps CPU, PCI clock skew 400ps (cycle to cycle) CPU jitter Smooth frequency switch , with selections from 50 to 83.3 MHz CPU. I2C interface for programming 2ms power up clock stable time Clock duty cycle 45-55%. 48 pin 300 mil SSOP package 3.3V operation, 5V tolerant input.
Pin Configuration
Block Diagram
48-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
Power Groups
VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK(0:5) VDD3 = SDRAM (0:11), supply for PLL core, 24MHz, 48MHz VDDL1 = IOAPIC VDDL2 = CPUCLK (0:3)
9148-08 Rev A 092297P
Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation
I C S reserves the right to make changes in the device data identified in this p u b l i c a t i o n without further notice. ICS advises its customers to obtain the latest v e r s i o n of all device data to verify that any information being relied upon by the c u s t o m e r is current and accurate.
ICS9148-08
Pin Descriptions
P I N NUMBER 1 P I N NAME V DD 1 R EF 0 TYPE PWR OUT DESCRIPTION R ef (0:1), XTAL power supply, nominal 3.3V 1 4 .3 1 8 MHz reference clock. I n d ic ates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU, L O W = 3 . 3 V CPU1 . Latched input2
2 3,9,16,22,27, 33,39,45 4 5 6, 14 7 8 10, 11, 12, 13 15 17, 18, 20, 21, 28, 29, 31, 32, 34, 35,37,38 19,30,36 23 24 25 26 40, 41, 43, 44 42
46
C P U 3 . 3 # _ 2 . 51 , 2 G ND X1 X2 V DD 2 PCICLK_F FS1 1 , 2 P C I C LK0 FS2 1 , 2 PCI CLK( 1:4) P C I C LK5
PCI_STOP#1 SDRAM (0:11) V DD 3 SDATA S C LK 2 4M H z M O DE 1 , 2 4 8M H z FS0 CPUCLK(0:3) V DD L2 REF1 CPU_STOP# 1
1, 2
IN PWR IN OUT PWR OUT IN OUT IN OUT OUT IN OUT PWR IN IN OUT IN OUT IN OUT PWR
O UT IN
G ro u n d C ry s ta l input, has internal load cap (33pF) and feedback r e s i s to r from X2 C ry s ta l output, nominally 14.318MHz. Has internal load ca p (33pF) S u p p l y for PCICLK_F and PCICLK (0:5), nominal 3.3V Free running PCI clock Frequency select pin. Latched Input PCI clock output. Frequency select pin. Latched Input PCI clock outputs. PCI clock output. (In desktop mode, MODE=1) Halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode, MODE=0)
SDRAM clock outputs. Supply for SDRAM (0:11), PLL core and 24,48MHz clocks, nominal 3.3V Data input for I2 C serial input. Clock input of I2 C input 24MHz output clock Pin 15, pin 46 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. 48MHz output clock Frequency select pin. Latched Input CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low Supply for CPU (0:3), either 2.5V or 3.3V nominal 14.318 MHz reference clock, (in Desktop Mode, MODE=1) This REF output is the STRONGER buffer for ISA BUS loads. Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in Mobile Mode, MODE=0) IOAPIC clock output. 14.318 MHz Powered by VDDL1. Supply for IOAPIC, either 2.5 or 3.3V nominal
47 48
I O A P IC VDDL1
OUT PWR
Notes: 1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic high to VDD or logic low to GND.
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ICS9148-08
Mode Pin - Power Management Input Control
MODE, Pin 25 (Latched Input) 0 1 Pin 46 CPU_STOP# (INPUT) REF1 (OUTPUT) Pin 15 PCI_STOP# (INPUT) PCICLK5 (OUTPUT)
Power Management Functionality
CPU_STOP# PCI_STOP# CPUCLK Outputs Stopped Low Running Running PCICLK (0:5) Running Running Stopped Low PCICLK_F, REF, 24/48MHz and SDRAM Running Running Running Crystal OSC Running Running Running VCO
0 1 1
1 1 0
Running Running Running
CPU 3.3#_2.5V Buffer selector for CPUCLK and IOAPIC drivers.
C P U 3 . 3 # _ 2 .5 I n p u t level (L a tc h e d Data) 1 0 B u ffe r Selected for o p e r a tio n at: 2 .5 V VDD 3 .3 V VDD
Functionality
FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1
VDD1,2,3 = 3.3V±5%, VDDL1,2 = 2.5V±5% or 3.3±5%, TA=0 to 70°C Crystal (X1, X2) = 14.31818MHz
FS0 0 1 0 1 0 1 0 1 CPU, SDR AM(M Hz) 5 0 .0 7 5 .0 8 3 .3 6 8 .5 5 5 .0 7 5 .0 6 0 .0 6 6 .8 PCIC LK (MHz) 25.0 (1/2 CPU) 30 (CPU/2.5) 33.3 34.25 (1/2 CPU) 27.5 (1/2 CPU) 37.5 (1/2 CPU) 30.0 (1/2 CPU) 33.4 (1/2 CPU) R E F, IOAPIC (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
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