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Details, datasheet, quote on part number:ICS9148-10
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS9148-10
Pentium/ProTM System Clock Chip
General Description
The ICS9148-10 is a Clock Synthesizer chip for Pentium and PentiumPro CPU based Desktop/Notebook systems that will provide all necessary clock timing. Features include four CPU and eight PCI clocks. Three reference outputs are available equal to the crystal frequency. A d d i t i o n a l l y, the device meets the Pentium power-up stabilization requirement, assuring that CPU and PCI clocks are stable within 2ms after power-up. PD# pin enables low power mode by stopping crystal OSC and PLL stages. Other power management features include CPU_STOP#, which stops CPU (0:3) clocks, and PCI_STOP#, which stops PCICLK (0:6) clocks. High drive CPUCLK outputs typically provide greater than 1 V/ns slew rate into 20pF loads. PCICLK outputs typically provide better than 1V/ns slew rate into 30pF loads while maintaining 50±5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. The ICS9148-10 accepts a 14.318MHz reference crystal or clock as its input and runs on a 3.3V core supply.
Features
Generates system clocks for CPU, IOAPIC, PCI, plus 14.314 MHz REF (0:2), USB, and Super I/O Supports single or dual processor systems Supports Spread Spectrum modulation for CPU & PCI clocks, down spread -1% Skew from CPU (earlier) to PCI clock (rising edges for 100/33.3MHz) 1.5 to 4ns Two fixed outputs at 48MHz. Separate 2.5V and 3.3V supply pins 2.5V or 3.3V output: CPU, IOAPIC 3.3V outputs: PCI, REF, 48MHz No power supply sequence requirements Uses external 14.318MHz crystal, no external load cap required for CL=18pF crystal 48 pin 300 mil SSOP
Block Diagram
Pin Configuration
48-Pin SSOP
Power Groups
VDD = Supply for PLL core VDD1 = REF (0:2), X1, X2 VDD2 = PCICLK_F, PCICLK (0:6) VDD3 = 48MHz0, 48MHz1 VDDL1 = IOAPIC (0:1) VDDL2 = CPUCLK (0:3)
9148-10 Rev D 9/27/99
Ground Groups
GND = Ground for PLL core GND1 = REF (0:2), X1, X2 GND2 = PCICLK_F, PCICLK (0:6) GND3 = 48MHz0, 48MHz1 GNDL1 = IOAPIC (0:1) GNDL2 = CPUCLK (0:3)
Pentium is a trademark on Intel Corporation.
I C S reserves the right to make changes in the device data identified in this p u b l i c a t i o n without further notice. ICS advises its customers to obtain the latest v e r s i o n of all device data to verify that any information being relied upon by the c u s t o m e r is current and accurate.
ICS9148-10
Pin Descriptions
PIN NUMBER 1, 2, 47 3 4 5 6, 12, 18 7 8, 10, 11, 13, 14, 16, 17 9, 15 19, 33 20, 32 21 22, 23 24 25 26, 27 28 29 30 31 37, 41 34, 38 35, 36, 39, 40 42 43 44, 45 46 48 PIN NAME REF (0:2) GND1 X1 X2 GND2 PCICLK_F PCICLK (0:6) VDD2 VDD GND VDD3 48MHz (0:1) GND3 SEL100/66.6# FS (0:1) SPREAD# PD# CPU_STOP# PCI_STOP# VDDL2 GNDL2 CPUCLK (3:0) N/C GNDL1 IOAPIC (0:1) VDDL1 VDD1 TYPE OU T PWR IN OUT PWR OUT OUT PWR PWR PWR PWR OU T PW R IN IN IN IN IN IN PWR PWR OU T PW R OUT PW R PWR DESCRIPTION 14.318MHz clock output Ground for REF outputs XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed back resistor from X2 XTAL_OUT Crystal output, has internal load cap 33pF Ground for PCI outputs Free Running PCI output PCI clock outputs. TTL compatible 3.3V Power for PCICLK outputs, nominally 3.3V Isolated power for core, nominally 3.3V Isolated ground for core Power for 48MHz outputs, nominally 3.3V 48MHz outputs Ground for 48MHz outputs Select pin for enabling 100MHz or 66.6MHz H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz) Frequency Select pins Enables Spread Spectrum feature when LOW Powers down chip, active low Halts CPU clocks at logic "0" level when low Halts PCI Bus at logic "0" level when low Power for CPU outputs, nominally 2.5V Ground for CPU outputs. CPU and Host clock outputs @ 2.5V Not internally connected Ground for IOAPIC outputs IOAPIC outputs (14.318MHz) @ 2.5V Power for IOAPIC outputs, nominally 2.5V Supply for REF (0:2), X1, X2, nominal 3.3V
Select Functions
Functionality Tristate Testmode Spread Spectrum CPU HI - Z TCLK/21 Modulated2 PCI, REF IOAPIC PCI_F HI - Z HI - Z HI - Z 1 1 TCLK/6 TCLK TCLK1 2 Modulated 14.318MHz 14.318MHz 48 MHz Selection HI - Z TCLK/21 48.0MHz
SEL 100/66# 0 0 0 0 1 1 1 1
FS1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1
Function Tri-State 59.73 74.63 Active 66.6MHz CPU, 33.3 PCI Test Mode 133.33 82.93 Active 100MHz CPU, 33.3 PCI
Notes: 1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode. 2. -1% modulation down spread from the selected frequency. 3. Performance not guaranteed
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ICS9148-10
Technical Pin Function Descriptions
VDD(1,2,3) This is the power supply to the internal core logic of the device as well as the clock output buffers for REF(0:2), PCICLK_F, PCICLK (0:6), 48MHz0, 48MHz1. This pin operates at 3.3V volts. Clocks from the listed buffers that it supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels for the Clocks, please consult the DC parameter table in this data sheet. VDDL1,2 This is the power supply for the CPUCLK (0:3) and IOAPIC output buffers. The voltage level for these outputs may be 2.5 or 3.3volts. Clocks from the buffers that each supplies will have a voltage swing from Ground to this level. For the actual Guaranteed high and low voltage levels of these Clocks, please consult the DC parameter table in this Data Sheet. GND (1,2,3) This is the ground to the internal core logic of the device as well as the clock output buffers for REF(0:2), PCICLK_F, PCICLK (0:6), 48MHz 0, 48MHz1. GNDL (1,2) This is the ground for the CPUCLK (0:3) and IOAPIC output buffers. X1 This input pin serves one of two functions. When the device is used with a Crystal, X1 acts as the input pin for the reference signal that comes from the discrete crystal. When the device is driven by an external clock signal, X1 is the device input pin for that reference clock. This pin also implements an internal Crystal loading capacitor that is connected to ground. With a nominal value of 33pF no external load cap is needed for a CL=17 to 18pF crystal. X2 This Output pin is used only when the device uses a Crystal as the reference frequency source. In this mode of operation, X2 is an output signal that drives (or excites) the discrete Crystal. The X2 pin will also implement an internal Crystal loading capacitor nominally 33pF. CPUCLK (0:3) These Output pins are the Clock Outputs that drive processor and other CPU related circuitry that requires clocks which are in tight skew tolerance with the CPU clock. The voltage swing of these Clocks is controlled by the Voltage level applied to the VDDL2 pin of the device. See the Functionality Table for a list of the specific frequencies that are available for these Clocks and the selection codes to produce them. 48MHz (0:1) This is a fixed frequency Clock output that is typically used to drive Super I/O devices. Outputs 0 and 1 are defined as 48MHz. IOAPIC (0:1) This Output is a fixed frequency Output Clock that runs at the Reference Input (typically 14.31818MHz) . Its voltage level swing is controlled by VDDL1 and may operate at 2.5 or 3.3volts. REF(0:2) The REF Outputs are fixed frequency Clocks that run at the same frequency as the Input Reference Clock X1 or the Crystal (typically 14.31818MHz) attached across X1 and X2. PCICLK_F This Output is equal to PCICLK(0:6) and is FREE RUNNING, and will not be stopped by PCI_STOP#. PCICLK (0:6) These Output Clocks generate all the PCI timing requirements for a Pentium/Pro based system. They conform to the current PCI specification. They run at 33.3 MHz. SELECT 100/66.6MHz# This Input pin controls the frequency of the Clocks at the CPUCLK, PCICLK and SDRAM output pins. If a logic 1 value is present on this pin, the 100MHz Clock will be selected. If a logic 0 is used, the 66.6MHz frequency will be selected. The PCI clock is multiplexed to be 33.3MHz for both select cases. PCI is synchronous at the rising edge of PCI to the CPU rising edge (with the skew making CPU early). PWR_DWN# This is an asynchronous active Low Input pin used to Power Down the device into a Low Power state by not removing the power supply. The internal Clocks are disabled and the VCO and Crystal are stopped. Powered Down will also place all the Outputs in a low state at the end of their current cycle. The latency of Power Down will not be greater than 3ms. CPU_STOP# This is a synchronous active Low Input pin used to stop the CPUCLK clocks in an active low state. All other Clocks including SDRAM clocks will continue to run while this function is enabled. The CPUCLKs will have a turn ON latency of at least 3 CPU clocks. PCI_STOP# This is a synchronous active Low Input pin used to stop the PCICLK clocks in an active low state. It will not affect PCICLK_F nor any other outputs.
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