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Details, datasheet, quote on part number:ICS9148-11
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS9148-11
Frequency Generator & Integrated Buffers for PENTIUMTM
General Description
T h e ICS9148-11 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro. An output enable pin is provided for testability. MODE allows power m a n a g e m e n t functions: CPU_STOP#, PCI_STOP# & PWR_DWN#. High drive BCLK outputs typically provide greater than 1V/ns slew rate into 30 pF loads. PCLK outputs typically provide better than 1V/ ns slew rate into 20 pF loads while maintaining 50± 5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates.
Features
Generates four processor, six bus, one 14.31818MHz and 12 SDRAM clocks. Synchronous clocks skew matched to 250ps window on CPU, SDRAM and 500ps window on BUS clocks. CPUCLKs to BUS clocks skew 1-4 ns (CPU early) Test clock mode eases system design Custom configurations available VDD(1:3) - 3.3V ±10% (inputs 5V tolerant w/series R ) VDDL(1:2) - 2.5V or 3.3V ±5% PC serial configuration interface Power Management Control Input pins 48-pin SSOP package
Block Diagram Pin Configuration
48-Pin SSOP
Functionality
OE C P UCL K, SDRAM ( MHz ) Hig h-Z 66 .6 X 1 , REF ( MHz ) P CI CLK ( MHz )
0 1
High- Z 14. 318
Hig h-Z 33.3
Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation 9148-11 RevB 12/09/97P
I C S reserves the right to make changes in the device data identified in this p u b l i c a t i o n without further notice. ICS advises its customers to obtain the latest v e r s i o n of all device data to verify that any information being relied upon by the c u s t o m e r is current and accurate.
ICS9148-11
Pin Descriptions
P I N NUMBER P I N NAME TYPE DES CRIPTIO N
2 3, 9, 16, 22, 27, 33, 39, 45 4 5 25 7 8, 10, 11, 12 13, 15 26 23 24 1, 6, 14, 19, 30, 36, 17, 18, 20, 21, 32, 34, 35, 37, 38 42, 48 40, 41, 43, 44 46, 47 28 29 31
REF0 GND X1 X2 MODE PCLK_F PCICLK (0:5) OE SDATA SCLK VDD1, VDD2, VDD3 SDRAM (0:4) (8:11) VDDL2, VDDL1 CPUCLK (0:3) IOAPIC (0:1) SDRAM7 P C I _ S TO P # SDRAM6 CP U _ S T O P # SDRAM5 PWR_DWN#
OUT P WR IN OUT IN OUT OUT IN IN IN P WR OUT P WR OUT OUT OUT IN OUT IN OUT IN
14.318 MHz reference clock outputs. Ground.
XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed back resistor from X2 XTAL_OUT Crystal output, has internal load cap 33pF
Mode select pin for enabling power management features. Free running BUS clock during PCI_STOP# = 0. BUS clock outputs.
Logic input for output enable, tristates all outputs when low. Serial data in for serial config port. Clock input for serial config port.
Nominal 3.3V power supply, see power groups for function. SDRAM clocks 66.6MHz. CPU and IOAPIC clock power supply, either 2.5 or 3.3V nominal CPU output clocks, powered by VDDL2 (66.6 MHz) IOAPIC clock output, (14.318 MHz) powered by VDDL1 SDRAM clock 66.6 MHz selected Halts PCICLK (0:5) at logic "0" level when low SDRAM clock 66.6 MHz selected Halts CPUCLK clocks at logic "0" level when low SDRAM clock 66.6 MHz selected Powers down chip, active low
Power Groups
VDD1 = REF0, X1, X2 VDD2 = PCICLK_F, PCICLK (0:5) VDD3 = SDRAM (0:4) (8:11) SDRAM5/PWR_DWN#, SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP#, supply for PLL Core. VDDL1 = IOAPIC (0:1) VDDL2 = CPUCLK (0:3)
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ICS9148-11
Power-On Conditions
MODE PIN # 44, 43, 41, 40 38, 37, 35, 34, 32, 31, 21, 20, 18, 17, 29, 28 8, 10, 11, 12, 14, 15, 7 28 29 31 0 7 44, 43, 41, 40 38, 37, 35, 34, 32, 21, 20, 18, 17 8, 10, 11, 12, 14, 15 DES CR I PT I ON CPUCLKs SDRAM PCICLKs PCI_STOP# CPU_STOP# SDRAM/PWR _DWN# PCICLK_F CPUCLKs SDRAM PCICLKs FU NCT I ON 66.6 MHz - w/serial config enable/disable 66.6 MHz - All SDRAM outputs 33.3 MHz - w/serial config enable/disable Power Management, PCI (0:5) Clocks Stopped when low Power Management, CPU (0:3) Clocks Stopped when low Used as PWR_DWN# when low 33.3 MHz - 33.3 MHz - PCI Clock Free running for Power Management 66.6 MHz - CPU Clocks w/external Stop Control and serial config individual enable/disable. 66.6 MHz - SDRAM Clocks w/serial config individual enable/disable. 33.3 MHz - PCI Clocks w/external Stop control and serial config individual enable/disable.
1
Example: a) if MODE = 1, pins 28, 29 and 31 are configured as SDRAM7, SDRAM6 and SDRAM5 respectively. b) if MODE = 0, pins 28, 29 and 31 are configured as PCI_STOP#, CPU_STOP# and PWR_DWN# respectively.
Power-On Default Conditions
At power-up and before device programming, all clocks will default to an enabled and on condition. The frequencies that are then produced are on the FS and MODE pin as shown in the table below.
C LO CK REF 0 I O A P I C (0:1)
D EF A U L T CONDITION AT POWER-UP 1 4 . 3 1 8 1 8 MHz 1 4 . 3 1 8 1 8 MHz
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