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Details, datasheet, quote on part number:ICS9148-26
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS9148-26
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9148-26 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Cyrix. Eight different reference frequency multiplying factors are externally selectable with smooth frequency transitions. Features include two CPU, six PCI and fourteen SDRAM clocks. Two reference outputs are available equal to the crystal frequency. Plus the IOAPIC output powered by VDDL1. One 48 MHz for USB, and one 24 MHz clock for Super IO. Spread Spectrum built in at ±0.5% or ±1.5% modulation to reduce the EMI. Serial programming I2C interface allows changing functions, stop clock programing and Frequency selection. A d d i t i o n a l l y, the device meets the Pentium power-up stabilization, which requires that CPU and PCI clocks be stable within 2ms after power-up. It is not recommended to use I/O dual function pin for the slots (ISA, PIC, CPU, DIMM). The add on card might have a pull up or pull down. High drive PCICLK and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs typically provide better than 1V/ns slew rate into 20pF loads while maintaining 50±5% duty cycle. The REF and 24 and 48 MHz clock outputs typically provide better than 0.5V/ns slew rates into 20pF.
Features
3.3V outputs: SDRAM, PCI, REF, 48/24MHz 2.5V outputs: CPU, IOAPIC 20 ohm CPU clock output impedance 20 ohm PCI clock output impedance Skew from CPU (earlier) to PCI clock - 1 to 4 ns, center 2.2 ns. No external load cap for CL=18pF crystals ±250 ps CPU, PCI clock skew 250ps (cycle to cycle) CPU jitter @ 66.66MHz Smooth frequency switch, with selections from 50 to 133 MHz CPU. I2C interface for programming 2ms power up clock stable time Clock duty cycle 45-55%. 48 pin 300 mil SSOP package 3.3V operation, 5V tolerant inputs (with series R) <6ns propagation delay SDRAM form Buffer Input
Pin Configuration
Block Diagram
48-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
Power Groups
VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK(0:4) VDD3 = SDRAM (0:13), supply for PLL core VDD4 = 24MHz, 48MHz VDDL1 = IOAPIC VDDL2 = CPUCLK (0:1)
9148-26 Rev D 07/23/98
Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation
I C S reserves the right to make changes in the device data identified in this p u b l i c a t i o n without further notice. ICS advises its customers to obtain the latest v e r s i o n of all device data to verify that any information being relied upon by the c u s t o m e r is current and accurate.
ICS9148-26
Pin Descriptions
P I N NUMBER 1 P I N NAME VD D 1 TYPE PWR DESCRIPTION Ref (0:2), XTAL power supply, nominal 3.3V 1 4.31 8 Mhz reference clock.This REF output is the STRONGER buffer for ISA BUS loads
2 3,9,16,22, 33,39,45 4 5 6,14 7 8 10, 11, 12, 13 15 18 17, 18, 20, 21, 28, 29, 31, 32, 34, 35,37,38,40,41 19,30,36 23 24 25 26 27 43, 44 42
46 17
RE F 0 GN D X1 X2 VD D 2 PCICLK_F
MODE1 , 2 PCICLK0 PCICLK(1:4) BUFFER IN PCI_STOP#1 SDRAM (0:13) VDD3 SDATA SCLK 24MHz FS11 , 2 48MHz FS01 , 2 VDD4 CPUCLK(0:1) VDDL2 REF1 FS21 , 2 CPU_STOP#1
OUT PWR IN OUT PWR OUT IN OUT OUT IN IN OUT PWR IN IN OUT IN OUT IN PWR OUT PWR OUT IN
IN
G r oun d Crystal input, has internal load cap (36pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (36pF) Su pply for PCICLK_F and PCICLK (0:5), nominal 3.3V Free running PCI clock Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. PCI clock output. PCI clock outputs. Input to Fanout Buffers for SDRAM outputs. Halts PCICLK(0:4) clocks at logic 0 level, when input low (In mobile mode, MODE=0) (Pins 17, 18 SDRAM output only if MODE=High) SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset). Supply for SDRAM (0:13) and CPU PLL Core, nominal 3.3V. Data input for I2 C serial input, 5V tolerant input Clock input of I2 C input, 5V tolerant input 24MHz output clock Frequency select pin. Latched Input. 48MHz output clock Frequency select pin. Latched Input Power for 24 & 48MHz output buffers and fixed PLL core. CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low Supply for CPU (0:1), either 2.5V or 3.3V nominal 14.318 MHz reference clock. Frequency select pin. Latched Input Halts CPUCLK (0:1) clocks at logic 0 level, when input low (in Mobile Mode, MODE=0) IOAPIC clock output. 14.318 MHz Powered by VDDL1. Supply for IOAPIC, either 2.5 or 3.3V nominal
47 48
IOAPIC VD DL1
OUT PWR
Notes: 1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
2
ICS9148-26
Mode Pin - Power Management Input Control
MODE, Pin 7 (Latched Input) 0 1 Pin 17 CPU_STOP# (INPUT) SDRAM11 (OUTPUT) Pin 18 PCI_STOP# (INPUT) SDRAM10 (OUTPUT)
Power Management Functionality
CPU_STOP# PCI_STOP# CPUCLK Outputs Stopped Low Running Running Stopped Low PCICLK (0:4) Running Running Stopped Low Stopped Low PCICLK_F, REF, 24/48MHz and SDRAM Running Running Running Running Crystal OSC Running Running Running Running VCO
0 1 1 0
1 1 0 0
Running Running Running Running
Functionality
VDD1,2,3 = 3.3V±5%, VDDL1,2 = 2.5V±5% or 3.3±5%, TA=0 to 70°C Crystal (X1, X2) = 14.31818MHz
FS2 1 1 1 1 0 0 0 0 FS1 1 1 0 0 1 1 0 0 FS0 1 0 1 0 1 0 1 0 CPU ( M H z) 1 0 0 .2 1 3 3 .3 1 11 2 . 0 1 103 66 .8 83 .3 75 50 P C IC LK ( M H z) 3 3 .3 (C P U /3 ) 3 3 . 3 (C P U /4 )1 3 7 . 3 (C P U /3 )1 3 4 .3 (C P U /3 ) 3 3 .4 (C P U /2 ) 4 1 . 6 5 (C P U /2 ) 3 7 .5 (C P U /2 ) 2 5 (C P U /2 ) R E F , IO A P I C ( M H z) 14 .3 1 8 14 .3 1 8 14 .3 1 8 14 .3 1 8 14 .3 1 8 14 .3 1 8 14 .3 1 8 14 .3 1 8
Note1. Performance not guaranteed
3
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