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Details, datasheet, quote on part number:ICS9148-27
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS9148-02
Pentium/ProTM System Clock Chip
General Description
The ICS9148-02 is a Clock Synthesizer chip for Pentium and PentiumPro CPU based Desktop/Notebook systems that will provide all necessary clock timing. Features include four CPU, seven PCI and eight SDRAM clocks. Two reference outputs are available equal to the crystal frequency. Additionally, the device meets the Pentium power-up stabilization, which requires that CPU and PCI clocks be stable within 2ms after power-up. PWR_DWN# pin allows low power mode by stopping crystal OSC and PLL stages. For optional power management, CPU_STOP# can stop CPU (0:3) clocks and PCI_STOP# will stop PCICLK (0:5) clocks. CPU and IOAPIC output buffer strength controlled by CPU 3.3_2.5# pin to match VDDL voltage. High drive CPUCLK outputs typically provide greater than 1 V/ns slew rate into 20pF loads. PCICLK outputs typically provide better than 1V/ns slew rate into 30pF loads while maintaining 50±5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. The ICS9148-02 accepts a 14.318MHz reference crystal or clock as its input and runs on a 3.3V core supply.
Features
Generates system clocks for CPU, IOAPIC, SDRAM, PCI, plus 14.314 MHz REF(0:1), USB, Plus Super I/O Supports single or dual processor systems I2C serial configuration interface provides output clock disabling and other functions MODE input pin selects optional power management input control pins Two fixed outputs separately selectable as 24 or 48MHz Separate 2.5V and 3.3V supply pins 2.5V or 3.3V outputs: CPU, IOAPIC 3.3V outputs: SDRAM, PCI, REF, 48/24 MHz CPU 3.3_2.5# logic pin to adjust output strength No power supply sequence requirements Uses external 14.318MHz crystal 48 pin 300 mil SSOP Output enable register for serial port control: 1 = enable 0 = disable
Pin Configuration
Block Diagram
48-Pin SSOP
VDD (1:4) 3.3V±10%, VDDL1, 2 2.5±5% or 3.3±10% 0-70°C Crystal (X1, X2) = 14.31818 MHz
SEL 0
Pentium is a trademark on Intel Corporation. 9148-02 Rev C 1/26/99
Functionality
CPUCLK, SDRAM (MHz) 60 66.6
PCICLK (MHz) 30 33.3
1
I C S reserves the right to make changes in the device data identified in this p u b l i c a t i o n without further notice. ICS advises its customers to obtain the latest v e r s i o n of all device data to verify that any information being relied upon by the c u s t o m e r is current and accurate.
ICS9148-02
Pin Descriptions
PIN NUMBER 2, 1 3, 10, 17, 24, 31, 37, 43 4 5 PIN NAME REF (0:1) GND X1 X2 TYPE OUT PWR IN OU T Ground (common) Crystal or reference input, has internal crystal load cap Crystal output, has internal load cap and feedback resistor to X1 Input function selection. If Mode is HIGH, then pins 26 & 27 are configured as outputs (SDRAM7 and SDRAM6). If Mode is LOW, then, pins 26 & 27 are configured as inputs (PCI_STOP# and CPU_STOP#). Supply for PCICLK_F, PCICLK (0:5), nominal 3.3V Free running PCI clock, not affected by PCI_STOP# PCI clocks Selects 60MHz or 66.6MHz for SDRAM and CPU I2C data input I2C clock input Supply for 48/24MHzA, 48/24MHzB, nominal 3.3V 48/24MHz driver output for USB or Super I/O 48/24MHz driver output for USB or Super I/O Supply for PLL core, nominal 3.3V SDRAM clock 60/66.6MHz (selected) Halts PCI Bus (0:5) at logic "0" level when low SDRAM clock 60/66.6MHz (selected) Halts CPU clocks at logic "0" level when low Supply for SDRAM (0:5), SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP#, nominal 3.3V Supply for CPUCLK (0:3), either 2.5 or 3.3V nominal CPUCLK clock output, powered by VDDL2 SDRAMs clock at 60 or 66.6MHz (selected) Powers down chip, active low IOAPIC clock output, (14.318MHz) powered by VDDL1 Supply for IOAPIC, either 2.5 or 3.3V nominal 3.3 or 2.5 VDD buffer strength selection, has pullup to VDD, nominal 30K resistor. When connected to VDD, 3.3V Buffer strength is selected. When connected to GND, 2.5V Buffer strength is selected. Supply for REF (0:1), X1, X2, nominal 3.3V DESCRIPTION Reference clock Output
6 7, 15 8 9, 11, 12, 13, 14, 16 18 19 20 21 22 23 25 26 27 28, 34 40 42, 41, 39, 38 36, 35, 33, 32, 30, 29 44 45 46 47 48
MODE VDD2 PCICLK_F PCICLK (0:5) SEL66/60# SDATA SCLK VDD4 48/24MHzA 48/24MHzB VDD SDRAM7 PCI_STOP# SDRAM6 CPU_STOP# VDD3 VDDL2 CPUCLK (0:3) SDRAM (0:5) PWR_DWN# IOAPIC VDDL1 CPU3.3-2.5# VDD1
IN PWR OUT OUT IN IN IN PWR OUT OUT PWR OUT IN OUT IN PWR PWR OUT OUT IN OUT PWR IN PWR
Power Groups
VDD = Supply for PLL core VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK (0:5) VDD3 = SDRAM (0:5), SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP# VDD4 = 48/24MHzA, 48/24MHzB VDDL1 = IOAPIC VDDL2 = CPUCLK (0:3)
2
ICS9148-02
Power-On Conditions
SEL 66/60# MODE PIN # 38, 39, 41, 42 36, 35, 33, 32, 30, 29, 27, 26 16, 14, 13, 12, 11, 9, 8 38, 39, 41, 42 36, 35, 33, 32, 30, 29, 27, 26 16, 14, 13, 12, 11, 9, 8 26 27 8 1 0 38, 39, 41, 42 36, 35, 33, 32, 30, 29 16, 14, 13, 12, 11, 9 26 27 8 0 0 38, 39, 41, 42 36, 35, 33, 32, 30, 29 16, 14, 13, 12, 11, 9 CPUCLKs SDRAM PCICLKs CPUCLKs SDRAM PCICLKs PCI_STOP# CPU_STOP# PCICLK_F DESCRIPTION CPUCLKs SDRAM PCICLKs CPUCLKs SDRAM PCICLKs PCI_STOP# CPU_STOP# PCICLK_F FUNCTION 66.6 MHz - w/serial config enable/disable 66.6 MHz - All SDRAM outputs 33.3 MHz - w/serial config enable/disable 60 MHz - w/serial config enable/disable 60 MHz - w/serial config enable/disable 30 MHz - w/serial config enable/disable Power Management, PCI (0:5) Clocks Stopped when low Power Management, CPU (0:5) Clocks Stopped when low 33.3 MHz - 33.3 MHz - PCI Clock Free running for Power Management 66.6 MHz - CPU Clocks w/external Stop Control and serial config individual enable/disable. 66.6 MHz - SDRAM Clocks w/serial config individual enable/disable. 33.3 MHz - PCI Clocks w/external Stop control and serial config individual enable/disable. Power Management, PCI (0:5) Clocks Stopped when low Power Management, CPU (0:5) Clocks Stopped when low 30 MHz - PCI Clock Free running for Power Management 60 MHz - CPU Clocks w/external Stop control and serial config individual enable/disable. 60 MHz - SDRAM Clocks w/serial config individual enable/disable. 30 MHz - PCI Clocks w/external Stop control and serial config individual enable/disable.
1
1
0
1
Example: a) if MODE = 1, pins 26 and 27 are configured as SDRAM7 and SDRAM6 respectively. b) if MODE = 0, pins 26 and 27 are configured as PCI_STOP# and CPU_STOP# respectively.
Power-On Default Conditions
At power-up and before device programming, all clocks will default to an enabled and on condition. The frequencies that are then produced are on the MODE pin as shown in the table below.
CLOCK REF (0:1) I OA P I C 0 48/24 MHz
D E FAU LT C O N D I T I O N AT P OW E R - U P 14.31818 MHz 14.31818 MHz 48 MHz
3
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