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Details, datasheet, quote on part number:ICS9148-36
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS9148-36
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9148-36 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Cyrix. Eight different reference frequency multiplying factors are externally selectable with smooth frequency transitions. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9148-36 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, s t o p clock programming and frequency selection. The SDRAM12 output may be used as a feed back into an off chip PLL.
Features
Generates the following system clocks: - 3 CPU(2.5V/3.3V) upto 100MHz. - 6 PCI(3.3V) @ 33.3MHz - 3AGP(3.3V) @ 2 x PCI - 13 SDRAMs(3.3V) up to 100MHz - 1 REF (3.3V) @ 14.318MHz Skew characteristics: - CPU CPU<250ps - CPU(early) PCI : 1-4ns, Center 2-6ns - AGP - PCI: 250ps Supports Spread Spectrum modulation & I2C programming for Power Management, Frequency Select Efficient Power management scheme through PCI and CPU STOP CLOCKS. Uses external 14.318MHz crystal 48 pin 300mil SSOP.
Block Diagram Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK(0:5) VDD3 = SDRAM (0:12), supply for PLL core VDD4 = AGP (1:2) VDD5 = Fixed PLL, 48MHz , AGP0 VDDL = CPUCLK (0:2)
9148-36 Rev I 11/11/99
48-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation
I C S reserves the right to make changes in the device data identified in this p u b l i c a t i o n without further notice. ICS advises its customers to obtain the latest v e r s i o n of all device data to verify that any information being relied upon by the c u s t o m e r is current and accurate.
ICS9148-36
Pin Descriptions
PIN NUMBER 1 2 3,9,16,22,27, 33,39,45 4 5 6 7 FS11, 2 8 10, 11, 12, 13 14 15 17 PCICLK0 FS21, 2 PCICLK(1:4) VDD5 BUFFERIN CPU_STOP#1 SDRAM 11 18 28, 29, 31, 32, 34, 35,37,38 20 PCI_STOP#1 SDRAM 10 SDRAM (0:9) AGP_STOP# SDRAM9 21 19,30,36 23 24 25 MODE1, 2 48MHz 26 41, 43, 44 40 42 46, 47 48 FS0
1, 2
P I N NA M E VDD1 REF0 C P U 3 . 3 # _ 2 . 5 1,2 GND X1 X2 VDD2 PCICLK_F
TYPE PWR OUT IN PWR IN OUT PWR OUT IN OUT IN OUT PWR IN IN OUT IN OUT OUT IN OUT IN OUT PWR IN IN OUT IN OUT IN OUT OUT PWR OUT PWR
DESCRIPTION Ref (0:2), XTAL power supply, nominal 3.3V 14.318 Mhz reference clock. Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V C P U 1. L a t c h e d i n p u t 2 Ground Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew (CPU early) This is not affected by PCI_STOP# Frequency select pin. Latched Input. Along with other FS pins determins the CPU, SDRAM, PCI & AGP frewuencies. PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early) Frequency select pin. Latched Input PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early) Supply for fixed PLL, 48MHz, AGP0 Input pin for SDRAM buffers. Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in Mobile Mode, MODE=0) SDRAM clock output Halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode, MODE=0) SDRAM clock output SDRAM clock outputs. This asynchronous input halts AGP(1:2) clocks at logic "0" level when input low (in Mobile Mode, MODE=0) Does not affect AGP0 SDRAM clock output This asyncheronous Power Down input Stops the VCO, crystal & internal clocks when active, Low. (In Mobile Mode, MODE=0) SDRAM clock output Supply for SDRAM (0:11), CPU Core, 48MHz clocks, nominal 3.3V. Data input for I2C serial input. Clock input of I2C input Advanced Graphic Port output, powered by VDD4. Not affected by AGP_STOP# Pin 17, 18, 20 & 21 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. 48MHz output clock for USB timing. Frequency select pin. Latched Input. Along with other FS pins determins the CPU, SDRAM, PCI & AGP frewuencies. CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low Feedback SDRAM clock output. Supply for CPU (0:3), either 2.5V or 3.3V nominal Advanced Graphic Port outputs, powered by VDD4. Supply for AGP (0:2)
PD# SDRAM8 VDD3 SDATA SCLK AGP0
CPUCLK(0:3) SDRAM12 VDDL AGP (1:2) VDD4
Notes: 1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
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ICS9148-36
Mode Pin - Power Management Input Control
MODE, Pin 25 (Latched Input) 0 1 Pin 17 CPU_STOP# (INPUT) SDRAM 11 (OUTPUT) Pin 18 PCI_STOP# (INPUT) SDRAM 10 (OUTPUT) Pin 20 AGP_STOP# (INPUT) SDRAM 9 (OUTPUT) Pin 21 PD# (INPUT) SDRAM 8 (OUTPUT)
Power Management Functionality
AGP_STOP# CPU_STOP# PCI_STOP# 1 1 1 0 0 1 1 1 1 1 0 1 AGP, CPUCLK Outputs Stopped Low Running Running Running PCICLK (0:5) Running Running Stopped Low Running PCICLK_F, REF, 48MHz and SDRAM Running Running Running Running Crystal OSC Running Running Running Running VCO Running Running Running Running AGP(1:2) Running Running Running Stopped Low
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5 Input level (Latched Data) 1 0 Buffer Selected for operation at: 2.5V VDD 3.3V VDD
Functionality
VDD1, 2, 3, 4 = 3.3V±5%, VDDL = 2.5V ±5% or 3.3 ±5%, TA= 0 to 70°C Crystal (X1, X2) = 14.31818MHz
FS2 1 1 1 1 0 0 0 0
FS1 1 1 0 0 1 1 0 0
FS0 1 0 1 0 1 0 1 0
CPU, SDRAM (MHz) 100 95.25 83.3 75 75 68.5 66.8 60
PCI (MHz) 33.3 31.75 33.3 30 37.5 34.25 33.4 30
AG P (MHz) 66.6 63.5 66.6 60 75 68.5 66.8 60
R E F, I OA P I C (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
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