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Details, datasheet, quote on part number:ICS9148-37
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS9148-37
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9148-37 is the single chip clock solution for Desktop/ Notebook designs using the VIA MVP3 style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9148-37 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. The SD_SEL latched input allows the SDRAM frequency to follow the C P U C L K frequency(SD_SEL=1) or the AGP clock frequency(SD_SEL=0)
Features
Generates the following system clocks: - 4 CPU(2.5V/3.3V) upto 100MHz. - 6 PCI(3.3V) @ 33.3MHz - 2AGP(3.3V) @ 2 x PCI - 12 SDRAMs(3.3V) @ either CPU or AGP - 2 REF (3.3V) @ 14.318MHz Skew characteristics: - CPU CPU<250ps - SDRAM SDRAM < 250ps - CPU SDRAM < 250ps - CPUAGP: < 1ns - CPU(early) PCI : 1-4ns Supports Spread Spectrum modulation +0.25, ±0.6% Serial I2C interface for Power Management, Frequency Select, Spread Spectrum. Efficient Power management scheme through PCI and CPU STOP CLOCKS. Uses external 14.318MHz crystal 48 pin 300mil SSOP.
Block Diagram
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK(0:5) VDD3 = SDRAM (0:11), supply for PLL core, 24 MHz, 48MHz VDD4 = AGP (0:1) VDDL = CPUCLK (0:3)
9148-37 Rev F 4/25/00
48-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation
I C S reserves the right to make changes in the device data identified in this p u b l i c a t i o n without further notice. ICS advises its customers to obtain the latest v e r s i o n of all device data to verify that any information being relied upon by the c u s t o m e r is current and accurate.
ICS9148-37
Pin Descriptions
PIN NUMBER 1 2 3,9,16,22,27, 33,39,45 4 5 6,14 7 FS11 , 2 PCICLK0 8 10, 11, 12, 13 15, 47 FS2
1, 2
P I N NA M E VDD1 REF0 CPU3.3#_2.51 , 2 GND X1 X2 VDD2 PCICLK_F
TYPE PWR OUT IN PWR IN OUT PWR OUT IN OUT IN OUT OUT IN OUT IN OUT OUT PWR IN IN OUT IN OUT IN OUT PWR OUT IN PWR
DESCRIPTION Ref (0:2), XTAL power supply, nominal 3.3V 14.318 MHz reference clock. Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V CPU1 . Latched input2 Ground Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew (CPU early) This is not affected by PCI_STOP# Frequency select pin. Latched Input. Along with other FS pins determines the CPU, SDRAM, PCI & AGP frequencies. PCI clock output. Synchronous CPUCLKs with 1-4ns skew (CPU early) Frequency select pin. Latched Input Along with other FS pins determines the CPU, SDRAM, PCI & AGP frequencies. PCI clock outputs. Synchronous CPUCLKs with 1-4ns skew (CPU early) Advanced Graphic Port outputs, powered by VDD4. This asynchronous input halts CPUCLK (0:3) and AGP (0:1) clocks at logic 0 level, when input low (in Mobile Mode, MODE=0) SDRAM clock output. Frequency is selected by the SD_SEL latched input. SD_SEL = 1 at power on causes SDRAM frequency = CPU frequency SD_SEL = 0 at power on causes SDRAM frequency = AGP frequency This asynchronous input halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode, MODE=0) SDRAM clock output. Frequency is selected by the SD_SEL latched input. SD_SEL = 1 at power on causes SDRAM frequency = CPU frenquency SD_SEL = 0 at power on causes SDRAM frequency = AGP frequency SDRAM clock outputs. Frequency is selected by the SD_SEL latched input. SD_SEL = 1 at power on causes SDRAM frequency = CPU frequency SD_SEL = 0 at power on causes SDRAM frequencies = AGP frequency Supply for SDRAM (0:11), CPU Core and 24, 48MHz clocks, nominal 3.3V. Data input for I2 C serial input. Clock input of I2 C input 24MHz output clock, for Super I/O timing. Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. 48MHz output clock, for USB timing. Frequency select pin. Latched Input Along with other FS pins determines the CPU, SDRAM, PCI & AGP frequencies. CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low Supply for CPU (0:3), either 2.5V or 3.3V nominal 14.318MHz reference clock. Latched input at Power On selects either CPU (SDSEL=1) or AGP (SD_SEL=0) frequencies for the SDRAM clock outputs. Supply for AGP (0:1)
PCICLK(1:4) AGP (0:1) CPU_STOP#1
17 SDRAM 11 PCI_STOP#1 18 SDRAM 10 20, 21,28, 29, 31, 32, 34, 35,37,38 19,30,36 23 24 25 SDRAM (0:9) VDD3 SDATA SCLK 24MHz MODE1 , 2 48MHz 26 40, 41, 43, 44 42 46 48 FS0
1, 2
CPUCLK(0:3) VDDL REF1 SD_SEL VDD4
Notes: 1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
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ICS9148-37
Mode Pin - Power Management Input Control
MO DE, Pin 25 (Latched Input) 0 1 Pin 17 CPU_STO P# (INPUT) SDRAM 11 (O UTPUT) Pin 18 PCI_STO P# (INPUT) SDRAM 10 (O UTPUT)
Power Management Functionality
CPU_STOP# PCI_STOP# AGP, CPUCLK Outputs Stopped Low Running Running PCICLK (0:5) Running Running Stopped Low PCICLK_F, REF, 24/48MHz and SDRAM Running Running Running Crystal OSC Running Running Running VCO
0 1 1
1 1 0
Running Running Running
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5 Input level (Latched Data) 1 0 Buffer Selected for operation at: 2.5V VDD 3.3V VDD
Functionality
VDD1, 2, 3, 4 = 3.3V±5%, VDDL = 2.5V ±5% or 3.3 ±5%, TA= 0 to 70°C Crystal (X1, X2) = 14.31818MHz
FS2 1 1 1 1 0 0 0 0 FS1 1 1 0 0 1 1 0 0 FS0 1 0 1 0 1 0 1 0 CPU (MHz) 100 95.25 83.3 75 75 68.5 66.8 60 SDRAM (MHz) SD_SEL=1 SD_SEL=0 100 66.6 95.25 63.5 83.3 66.6 75 60 75 75 68.5 68.5 66.8 66.8 60 60 PCI (MHz) 33.3 31.75 33.3 30 37.5 34.25 33.4 30 AG P ( M H z ) 66.6 63.5 66.6 60 75 68.5 66.8 60
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