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Details, datasheet, quote on part number:ICS9148-46
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS9148-46
Pentium/ProTM System Clock Chip
General Description
The ICS9148-46 is part of a reduced pin count two-chip clock s o l u t i o n for designs using an Intel BX style chipset. Companion SDRAM buffers are ICS9179-03, and -12. There are two PLLs, with the first PLL capable of spread spectrum operation. Spread spectrum typically reduces system EMI by 8-10dB. The second PLL provides support for USB (48MHz) and 24MHz requirements. CPU frequencies up to 100MHz are supported. The I2C interface allows stop clock programming, frequency selection, and spread spectrum operation to be programmed. Clock outputs include two CPU (2.5V or 3.3V), five PCI (3.3V), two REF (3.3V), one 48MHz, and one selectable 48_24MHz.
Features
Generates system clocks for CPU, PCI, 14.314 MHz, 48 and 24MHz. Supports single or dual processor systems Skew from CPU (earlier) to PCI clock 1 to 4ns Separate 2.5V and 3.3V supply pins 2.5V outputs: CPU 3.3V outputs: PCI, REF No power supply sequence requirements 28 pin SSOP Spread Sectrum operation optional for PLL1 CPU frequencies to 100MHz are supported.
Block Diagram
Pin Configuration
28 pin SSOP
Power Groups
VDD = Supply for PLL core VDD1 = REF(0:1), X1, X2 VDD2 = PCICLK_F, PCICLK (0:3) VDD3 = 48MHz, 24/48MHz VDDL = CPUCLK (0:1)
Ground Groups
GND = Ground Source Core, CPUCLK (0:1) GND1 = REF(0:1), X1, X2 GND2 = PCICLK_F, PCICLK (0:5) GND3=48MHz, 24/48MHz
Pentium is a trademark on Intel Corporation. 9148-46 Rev E 4/20/99
I C S reserves the right to make changes in the device data identified in t h i s publication without further notice. ICS advises its customers to o b t a i n the latest version of all device data to verify that any i n f o r m a t i o n being relied upon by the customer is current and accurate.
ICS9148-46
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6, 7, 9, 10 8 11 12 13 14 15 16 17 18 19 20 21 22 23, 24 25 26 27 28 PIN NAME GND1 X1 X2 GND2 PCICLK_F PCICLK (0:3) VDD2 VDD3 48MHz 24_48MHz GND3 SEL100/66.6# SCLK SDATA PD# CPU_STOP# PCI_STOP# GN D VDD CPUCLK (1:0) VDDL REF1 VDD1 REF0 SEL 48# TYPE PW R IN OUT PWR OUT OUT PWR PWR OUT OUT PWR IN IN IN IN IN IN PWR PWR OUT PWR OUT PW R OUT IN DESCRIPTION Ground for REF (0:1), X1, X2. XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed back resistor from X2 XTAL_OUT Crystal output, has internal load cap 33pF Ground for PCI outputs Free Running PCI output. Not affected by PCI_STOP# PCI clock outputs. TTL compatible 3.3V Power for PCICLK outputs, nominally 3.3V Poer for 48MHz Fixed CLK output @ 48MHz Fixed CLK output; 24MHz if pin 27 =1 at power up, 48MHz if pin 27=0 at power up. Ground for 48MHz Select pin for enabling 100MHz or 66.6MHz H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz) Clock input for I2C input Data input for I2C input Asynchronous input when driven active (LOW) disables internal clocks, stops VCO early. All outputs are placed in a LOW state at the end of the curent cycle. Asynchronous input when driven active (LOW) stops CPUCLK(0:1) in a LOW state. Asynchronous input when driven active (LOW) stops PCICLK(0:3) in a LOW state. PCICLK_F is not affected. Ground for CPUCLK (0:1) and the core Power for PLL core CPU and Host clock outputs nominally 2.5V Power for CPU outputs, nominally 2.5V 14.318MHz Reference clock output Power for REF outputs. 14.318MHz clock output Latched input at power up. When low, pin 13 is 48MHz.
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ICS9148-46
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ICS (Slave/Receiver)
How to Read:
Controller (host) will send start bit. Controler (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
ACK
Byte 1
Byte 1
ACK
ACK
Byte 2
Byte 2
ACK
ACK
Byte 3
Byte 3
ACK
ACK
Byte 4
Byte 4
ACK
ACK
Byte 5
Byte 5
ACK
ACK
Byte 6
Byte 6
ACK
ACK Stop Bit
Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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