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Details, datasheet, quote on part number:ICS9148-47
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS9148-47
Pentium/ProTM System Clock Chip
General Description
The ICS9148-47 is part of a reduced pin count two-chip clock s o l u t i o n for designs using an Intel BX style chipset. Companion SDRAM buffers are ICS9179-11 and 12. There are two PLLs, with the first PLL capable of spread spectrum operation. Spread spectrum typically reduces system EMI by 8-10dB. The second PLL provides support for USB (48MHz) and 24MHz requirements. CPU frequencies up to 100MHz are supported. The I2C interface allows stop clock programming, frequency selection, and spread spectrum operation to be programmed. Clock outputs include two CPU (2.5V or 3.3V), seven PCI (3.3V), one REF (3.3V), one IOAPIC (2.5V or 3.3V), one 48MHz, and one selectable 48/24MHz.
Features
Generates system clocks for CPU, PCI, IOAPIC , 14.314 MHz, 48 and 24MHz. Supports single or dual processor systems Skew from CPU (earlier) to PCI clock 1 to 4ns Separate 2.5V and 3.3V supply pins 2.5V outputs: CPU, IOAPIC 3.3V outputs: PCI, REF No power supply sequence requirements 28 pin SOIC Spread Sectrum operation optional for PLL1 CPU frequencies to 100MHz are supported.
Pin Configuration Block Diagram
28 pin SOIC
Power Groups
VDD = Supply for PLL core VDD1 = REF0, X1, X2 VDD2 = PCICLK_F, PCICLK (0:5) VDD3 = 48MHz VDDL = CPUCLK (0:1) VDDL1=IOAPIC
Ground Groups
GND = Ground Source Core GND1 = REF0, X1, X2 GND2 = PCICLK_F, PCICLK (0:5) GND3=48MHz GNDL = CPUCLK (0:1)
Pentium is a trademark on Intel Corporation. 9148-47 Rev D 08/04/98
I C S reserves the right to make changes in the device data identified in this p u b l i c a t i o n without further notice. ICS advises its customers to obtain the latest v e r s i o n of all device data to verify that any information being relied upon by the c u s t o m e r is current and accurate.
ICS9148-47
Pin Descriptions
PIN NUMBER 1 2 3 4 5, 6, 7, 8, 10, 11 6, 9 12 13 14 15 16 17 18 19 20 21, 22 23 24 25 26 27 28 PIN NAME X1 X2 GND2 PCICLK_F PCICLK (0:5) V DD2 VDD3 48MHz 24/48MHz G ND3 SEL100/66.6# SCLK SDATA G ND VDD CPUCLK (1:0) VDDL IOAPIC VDDL VD D1 REF0/SEL 48# GND 1 TYPE IN O UT PWR O UT O UT PWR PWR O UT O UT PW R IN IN IN PWR PW R O UT PWR O UT PWR PWR OUT/IN PWR DESCRIPTION XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed back resistor from X2 XTAL_OUT Crystal output, has internal load cap 33pF Ground for PCI outputs Free Running PCI output PCI clock outputs. TTL compatible 3.3V Power for PCICLK outputs, nominally 3.3V Poer for 48MHz Fixed CLK output @ 48MHz Fixed CLK output; 24MHz if pin 27 =1 at power up, 48MHz if pin 27=0 at power up. Ground for 48MHz Select pin for enabling 100MHz or 66.6MHz H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz) Clock input for I2C input Data input for I2C input Ground for CPUCLK (0:1) Power for PLL core CPU and Host clock outputs nominally 2.5V Power for CPU outputs, nominally 2.5V IOAPIC clock output 14.318MHz. Power for IOAPIC Power for REF outputs. 14.318MHz clock output/Latched input at power up. When low, pin 14 is 48MHz. Ground for REF outputs, X1, X2.
2
ICS9148-47
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Send the address D2(H) . Send two additional dummy bytes, a command code and byte count. Send the desired number of data bytes.
See the diagram below:
Clock Generator Address (7 bits) + 8 bits dummy command code + 8 bits dummy Byte count Data Byte 1 Data Byte N
A(6:0) & R/W# D2(H)
ACK
ACK
ACK
ACK
ACK
Note that the acknowledge bit is sent by the clock chip, and pulls the data line low. There is no minimum of data bytes that must be sent.
How to Read:
Send the address D3(H). Send the byte count in binary coded decimal Read back the desired number of data bytes
See the diagram below:
Clock Generator Address (7 bits) A(6:0) & R/W# D3(H) ACK
Byte Count
ACK
Data Byte 1
ACK
Data Byte N
The following specifications should be observed: 1. Operating voltage for I2C pins is 3.3V 2. Maximum data transfer rate (SCLK) is 100K bits/sec.
3
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