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Details, datasheet, quote on part number:ICS9169F-01
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS9169-01
Frequency Generator and Integrated Buffers for Intel Pentium and Pentium ProTM µP's
General Description
The ICS9169-01 generates all clocks required for high speed RISC or CISC microprocessor systems such as 486, Pentium/ Pentium ProTM, PowerPCTM, etc. Four different reference frequency multiplying factors are externally selectable with smooth frequency transitions. These multiplying factors can be customized for specific applications. A test mode is provided to drive all clocks directly. High drive BCLK outputs typically provide greater than 1V/ ns slew rate into 30pF loads. PCLK outputs typically provide better than 1V/ns slew rate into 20pF loads while maintaining 50±5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates.
Features
· Generates four processor, six bus, three 14.318 MHz and one 48 MHz clock for ISA bus, audio, super I/O and bus bridge devices Supports the Intel MARS chip set Synchronous clocks skew matched to 250ps window on PCLKs and 500ps window on BCLKs Test clock mode eases system design Selectable multiplying ratios Custom configurations available Output frequency ranges to 100 MHz (depending on option) 3.0V - 5.5 V supply range 28-pin SOIC and 28-pin SSOP (209-mil) packages
· · · · · · · ·
Applications
· Ideal for high-speed RISC or CISC systems such as 486, Pentium, Pentium Pro, PowerPC, etc.
Block Diagram
PLL CLOCK GEN
48 MHz
X2 X1
XTAL OSC
REF(0:2) OEN
FS0 FS1
PLL CLOCK GEN
SYNC REG
PCLK(0:3) BCLK(0:5)
P e n t i u m is a trademark of Intel Corporation P o w e r P C is a trademark of Motorola Corporation 9169-01RevE 08/28/98
I C S reserves the right to make changes in the device data identified in this publication w i t h o u t further notice. ICS advises its customers to obtain the latest version of all d e v i c e data to verify that any information being relied upon by the customer is current a n d accurate.
ICS9169-01
Pin Configuration
Functionality
FS1 0 0 1 1 FS0 0 1 0 1 *VCO 230/33x X1 212/23x X1 176/21x X1 Test mode X1, REF (MHz ) 14.31818 14.31818 14.31818 TCLK PCLK(0:3) (MHz) 50 (49.7) 66 (66.5) 60 (59.9) TCLK/2
*VCO range is limited from 60 - 200 MHz
PCLK(0:3) VCO/2 TCLK/2 BCLK(0:5) PCLK/2 TCLK/4 48 MHz 48 MHz TCLK/2
28 Pin SOIC 28 Pin SSOP Pin Descriptions
P IN NUMBER 2 3 4 , 11, 23 17 1 , 8, 26 1 4 , 20 6 , 7, 9, 10 1 3 , 12 1 5 , 16, 18 1 9 , 21, 22 5 24 2 8 , 27, 25 P I N NAME X1 X2 GND GND VDD VDD P C L K ( 0 :3 ) F S ( 0 :1 ) B C L K (0 :5) OEN 48 M H z R E F ( 0 :2 ) TYPE IN OUT PW R PW R PW R PW R OUT IN OUT IN OUT OUT D E S C R IPT IO N X TA L or external reference frequency input. This input includes XTAL load cap acitan ce and feedback bias for a 12.16 MHz crystal, nominally 14.31818 X TA L output which includes XTAL load capacitance. G ro u n d for logic, PCLK and fixed frequency output buffers. G ro u n d for BCLK output buffers. P o w er for logic, PCLK and fixed frequency output buffers. P o w er for BCLK output buffers. P ro cess o r clock outputs which are a multiple of the input reference frequency as shown in the table above. F re q u e n c y multiplier select pins. See table above. These inputs have internal p u ll-u p devices. B u s clock outputs are fixed at 1/2 the PCLK frequency. O E N tristates all outputs when low. This input has an internal pull-up device. F ix ed 48 MHz clock (with 14.318 MHz input). R E F is a buffered copy of the crystal oscillator or reference input clock, n o m in a lly 14.31818 MHz.
Note 1: BCLK buffers cannot be supplied with 5 volts (pins 14 and 20) if CPU and fixed frequencies (pins 1, 8, and 26) are being supplied with 3.3 volts
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ICS9169-01
Absolute Maximum Ratings
Supply Voltage......... 7.0 V Logic Inputs .......... GND - 0.5 V to VDD + 0.5 V . Ambient Operating Temperature ......... 0 to +70 C Storage Temperature ........ -65 to +150 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stess specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Stresses a stess spec operation periods m
Electrical Characteristics at 3.3 V
VDD = 3.0 - 3.7 V, TA = 0 - 70oC unless otherwise stated
DC Characteristics
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current1 Output High Current1 Output Low Current1 Output High Current1 Output Low Voltage1 Output High Voltage1 Output Low Voltage1 Output High Voltage1 Supply Current
SYMBOL VIL VIH IIL IIH IOL IOH IOL IOH VOL VOH VOL VOH IDD
TEST CONDITIONS
MIN 0.7VDD
TYP -10.5 47.0 -66.0 38.0 -47.0 0.3 2.8 0.3 2.8 55
MAX 0.2VDD 5.0 -42.0 -30.0 0.4 0.4 110
UNITS V V
µA µA
VIN = 0 V VIN = VDD VOL = 0.8 V; for PCLKs & BCLKs VOL = 2.0 V; for PCLKs & BCLKs VOL=0.8V; for fixed CLKs VOL=2.0V; for fixed CLKs IOL = 15 mA; for PCLKs & BCLKs IOH = -30 mA; for PCLKs & BCLKs IOL=12.5mA; for fixed CLKs IOH = -20mA; for fixed CLKs @ 66.5 MHz; all outputs unloaded
-28.0 -5.0 30.0 25.0 2.4 2.4 -
mA mA mA mA V V V V mA
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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