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Details, datasheet, quote on part number:ICS91718yM
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS91718
Low EMI, Spread Modulating, Clock Generator
Features: · ICS91718 is a Spread Spectrum Clock targeted for Mobile PC and LCD panel applications. Generates an EMI optimized clock signal (EMI peak reduction of 7-14 dB on 3rd-19th harmonics) through use of Spread Spectrum techniques. · ICS91718 operates with input frequencies at 14.318 - 80 MHz. · Spread modulation frequency range is 20kHz to 40kHz. · Spread percentage/type programming through I 2C . Specifications: · Supply Voltages: VDD = 3.3V ±0.3V · Cyc to Cyc jitter: <150ps · Output duty cycle 45/55% · Guarantees +85°C operational condition · 8-pin SOIC (150 mil) package
Pin Configuration
CLKIN VDD GND **CLKOUT/ FS_I N0
1 2 3 4 8 7 6 5
PD#* SCLK SDATA REF_OUT/ FS_I N1**
8-pin SOIC
Notes: * Internal pull-up resistor ** Internal pull-down resistor
Input Select Functionality
FS_IN 1 FS_IN 0
0 0 1 1 0 1 0 1
MH z
14.318 in 48.00 out 14.318 in 66.66 out 48.00 in/out 66.66 in/out 48.00 in/out 66.66 in/out
SPREAD %
-1.0% down sprd -1.0% down sprd -1.0% down sprd +/-1.0% center sprd
Block Diagram
REFOUT CLKIN PLL1 Spread Spectrum CLKOUT
PD# FS_IN0:1 SDATA SCLK
Control Logic Config. Reg.
0500B--02/13/03
ICS91718
Pin Descriptions
PIN # 1 2 3 4 5 6 7 8 PIN NAME CLKIN VDD GND **CLKOUT/FS_IN0 REF_OUT/FS_IN1** SDATA SCLK PD#* PIN DESCRIPTION TYPE IN Input clock PWR Power supply, nominal 3.3V PWR Ground pin. CLKOUT modulated clock output I/O FS_IN0 latched input, selects modulation percentage/type REF_OUT, unmodulated reference clock output I/O FS_IN1 latched input, selects modulation percentage/type I/O Data pin for I2C circuitry 5V tolerant IN Cloc k pin of I2C circuitry 5V tolerant As y nc hronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the IN crystal are stopped. The latency of the power down will not be greater than 1.8ms.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor
0500B--02/13/03
2
ICS91718
Table 1: Frequency Configuration Table (See I2C Byte 0)
FS 4 FS 3 FS 2 FS 1 FS 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 Sprd Type Sprd % 0.80 1.00 DOWN 1.25 SP READ 1.50 (-) 1.75 2.00 2.50 0.60 CENTER 1.00 SP READ 1.25 (+ /-) 1.50 2.00 1.25 DOWN 1.00 SP READ 1.50 (-) 2.00 0.80 1.00 1.25 DOWN 1.50 SP READ 1.75 (-) 2.00 2.50 3.00 0.30 0.40 0.50 CENTER 0.60 SP READ 0.80 (+ /-) 1.00 1.25 1.50
14in/48out
14in/66out
48in/48out 66in/66out
For 14.318 in 48.008 out default is...00001 .. For 14.318 in 66.66 out default is... 1101 ... 0 For 48/48 and 66/66 default is... .10001 ... ...
0500B--02/13/03
3
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